diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index e5ce2b407..3bae29f52 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1137,22 +1137,6 @@ RTLIL::Module *RTLIL::Design::top_module() const
 	return module_count == 1 ? module : nullptr;
 }
 
-void RTLIL::Design::add(RTLIL::Module *module)
-{
-	log_assert(modules_.count(module->name) == 0);
-	log_assert(refcount_modules_ == 0);
-	modules_[module->name] = module;
-	module->design = this;
-
-	for (auto mon : monitors)
-		mon->notify_module_add(module);
-
-	if (yosys_xtrace) {
-		log("#X# New Module: %s\n", log_id(module));
-		log_backtrace("-X- ", yosys_xtrace-1);
-	}
-}
-
 void RTLIL::Design::add(RTLIL::Binding *binding)
 {
 	log_assert(binding != nullptr);
diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc
index d4f85c789..a9a5f542c 100644
--- a/kernel/rtlil_bufnorm.cc
+++ b/kernel/rtlil_bufnorm.cc
@@ -1203,4 +1203,25 @@ void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal
 
 }
 
+void RTLIL::Design::add(RTLIL::Module *module)
+{
+	log_assert(modules_.count(module->name) == 0);
+	log_assert(refcount_modules_ == 0);
+	modules_[module->name] = module;
+	module->design = this;
+
+	for (auto mon : monitors)
+		mon->notify_module_add(module);
+
+	if (yosys_xtrace) {
+		log("#X# New Module: %s\n", log_id(module));
+		log_backtrace("-X- ", yosys_xtrace-1);
+	}
+
+	if (flagSigNormalized) {
+		module->sigNormalize();
+	}
+
+}
+
 YOSYS_NAMESPACE_END