From 64f6b0c747eb915be9205b36bd69745a2385aea1 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Fri, 28 Jun 2019 13:41:32 -0700 Subject: [PATCH 1/7] Try command in another module --- tests/various/script.ys | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tests/various/script.ys b/tests/various/script.ys index 6044ad9b3..9ccc727eb 100644 --- a/tests/various/script.ys +++ b/tests/various/script.ys @@ -6,6 +6,9 @@ read_verilog -formal < Date: Mon, 1 Jul 2019 09:46:56 -0700 Subject: [PATCH 2/7] Move CHANGELOG entry from yosys-0.8 to 0.9 --- CHANGELOG | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index b54897d89..818225e56 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,13 +2,6 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.9 .. Yosys 0.9-dev --------------------------- - - * Various - - Added "script -select" - - Yosys 0.9 .. Yosys 0.9-dev -------------------------- @@ -18,6 +11,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Added "synth -abc9" (experimental) + - Added "script -select" Yosys 0.8 .. Yosys 0.8-dev From 6282a67332e9ca0ffe68b7ae57e93b6248946d4a Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 1 Jul 2019 11:59:10 -0700 Subject: [PATCH 3/7] Space --- CHANGELOG | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG b/CHANGELOG index 818225e56..4348b3d7a 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,7 @@ List of major changes and improvements between releases ======================================================= + Yosys 0.9 .. Yosys 0.9-dev -------------------------- From 02ba85b13302f0d20f6b51cc7fdff2fb953421df Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 2 Jul 2019 08:17:26 -0700 Subject: [PATCH 4/7] script -select -> script -scriptwire --- CHANGELOG | 2 +- kernel/yosys.cc | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/CHANGELOG b/CHANGELOG index 4348b3d7a..ae7d28236 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -12,7 +12,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Added "synth -abc9" (experimental) - - Added "script -select" + - Added "script -scriptwire Yosys 0.8 .. Yosys 0.8-dev diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 7d4948881..456ad48a0 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1259,7 +1259,7 @@ struct ScriptCmdPass : public Pass { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" script [:]\n"); - log(" script -select [selection]\n"); + log(" script -scriptwire [selection]\n"); log("\n"); log("This command executes the yosys commands in the specified file (default\n"); log("behaviour), or commands embedded in the constant text value connected to the\n"); @@ -1276,17 +1276,17 @@ struct ScriptCmdPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { - bool select_mode = false; + bool scriptwire = false; size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - if (args[argidx] == "-select") { - select_mode = true; + if (args[argidx] == "-scriptwire") { + scriptwire = true; continue; } break; } - if (select_mode) { + if (scriptwire) { extra_args(args, argidx, design); for (auto mod : design->selected_modules()) From 90382a0f6d1ad7dfd14ced95051e5e76de89491c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 2 Jul 2019 08:19:23 -0700 Subject: [PATCH 5/7] Update test too --- tests/various/script.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/various/script.ys b/tests/various/script.ys index 9ccc727eb..4152145e8 100644 --- a/tests/various/script.ys +++ b/tests/various/script.ys @@ -13,8 +13,8 @@ read_verilog -formal < Date: Tue, 2 Jul 2019 08:20:37 -0700 Subject: [PATCH 6/7] Use Pass::call_on_module() as per @cliffordwolf comments --- kernel/yosys.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 456ad48a0..f95c0127b 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -1299,7 +1299,7 @@ struct ScriptCmdPass : public Pass { if (!c.second.is_fully_const()) log_error("RHS of selected wire %s.%s is not constant.\n", log_id(mod), log_id(w)); auto v = c.second.as_const(); - Pass::call(design, v.decode_string()); + Pass::call_on_module(design, mod, v.decode_string()); } } else if (args.size() < 2) From 81a717e9b767792f64535757f905a5061c627fbd Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Tue, 2 Jul 2019 08:22:31 -0700 Subject: [PATCH 7/7] Update test for Pass::call_on_module() --- tests/various/script.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/various/script.ys b/tests/various/script.ys index 4152145e8..66b7b5caa 100644 --- a/tests/various/script.ys +++ b/tests/various/script.ys @@ -9,7 +9,7 @@ read_verilog -formal <