mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-21 16:16:39 +00:00
Code Activity

speedup

Browse source
This commit is contained in:
Alain Dargelas 2025-03-04 11:09:09 -08:00
parent 3e25ff70ee
commit 864850ab51
1 changed files with 18 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
passes/silimate/annotate_cell_fanout.cc
View file

@ -517,6 +517,8 @@ void splitNet(Design *design, std::set<std::string> &netsToSplitS, RTLIL::SigSpe
if (parent == "") {
return;
}
if (parentWire->width == 1)
return;
parent = substringuntil(parent, '[');
if (netsToSplitS.find(parent) == netsToSplitS.end()) {
netsToSplitS.insert(parent);
@ -604,8 +606,14 @@ struct AnnotateCellFanout : public ScriptPass {
Cell *cell = itrCell.first;
int fanout = itrCell.second;
if (limit > 0 && (fanout > limit)) {
RTLIL::SigSpec cellOutSig = getCellOutputSigSpec(cell, sigmap);
splitNet(design, netsToSplitS, cellOutSig, formalFriendly);
for (auto &conn : cell->connections()) {
IdString portName = conn.first;
RTLIL::SigSpec actual = conn.second;
if (cell->output(portName)) {
RTLIL::SigSpec cellOutSig = sigmap(actual);
splitNet(design, netsToSplitS, cellOutSig, formalFriendly);
}
}
}
}
@ -640,8 +648,14 @@ struct AnnotateCellFanout : public ScriptPass {
Cell *cell = itrCell.first;
int fanout = itrCell.second;
if (limit > 0 && (fanout > limit)) {
RTLIL::SigSpec cellOutSig = getCellOutputSigSpec(cell, sigmap);
fixfanout(module, sigmap, sig2CellsInFanout, cellOutSig, fanout, limit, debug);
for (auto &conn : cell->connections()) {
IdString portName = conn.first;
RTLIL::SigSpec actual = conn.second;
if (cell->output(portName)) {
RTLIL::SigSpec cellOutSig = sigmap(actual);
fixfanout(module, sigmap, sig2CellsInFanout, cellOutSig, fanout, limit, debug);
}
}
fixedFanout = true;
} else {
// Add attribute with fanout info to every cell