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Code Activity

ABC9: Cell Port Bug Patch (#3670)

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* ABC9: RAMB36E1 Bug Patch

* Add simplified testcase

* Also fix xaiger writer for under-width output ports

* Remove old testcase

* Missing top-level input port

* Fix tabs

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Co-authored-by: Eddie Hung <eddie@fpgeh.com>
This commit is contained in:
Benjamin Barzen 2023-04-23 01:24:36 +02:00 • committed by GitHub
parent 7efc50367e
commit 8611429237
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GPG key ID: 4AEE18F83AFDEB23
4 changed files with 26 additions and 2 deletions
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tests/arch/xilinx/bug3670.ys Normal file
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read_verilog bug3670.v
read_verilog -lib -specify +/xilinx/cells_sim.v
abc9