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* ABC9: RAMB36E1 Bug Patch * Add simplified testcase * Also fix xaiger writer for under-width output ports * Remove old testcase * Missing top-level input port * Fix tabs --------- Co-authored-by: Eddie Hung <eddie@fpgeh.com>
4 lines
76 B
Plaintext
4 lines
76 B
Plaintext
read_verilog bug3670.v
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read_verilog -lib -specify +/xilinx/cells_sim.v
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abc9
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