mirror of
https://github.com/YosysHQ/yosys
synced 2026-07-24 16:12:33 +00:00
autoname: selection determines what gets renamed, not the name it gets renamed to
This commit is contained in:
parent
fb0bb160ad
commit
8565451ef9
2 changed files with 60 additions and 27 deletions
|
|
@ -78,12 +78,21 @@ module \top
|
|||
end
|
||||
end
|
||||
EOT
|
||||
design -save fanout_test
|
||||
logger -expect log "Rename cell .name in top to bcd_.and_B" 1
|
||||
logger -expect log "Rename cell .name2 in top to c_has_a_long_name_.or_B" 1
|
||||
logger -expect log "Renamed 2 objects" 1
|
||||
debug autoname
|
||||
logger -check-expected
|
||||
|
||||
# a selection only limits what gets renamed, never the name that gets picked:
|
||||
# \a's fanout still counts $name2, even though it isn't selected
|
||||
design -load fanout_test
|
||||
logger -expect log "Rename cell .name in top to bcd_.and_B" 1
|
||||
logger -expect log "Renamed 1 objects" 1
|
||||
debug autoname c:$name
|
||||
logger -check-expected
|
||||
|
||||
# names are unique
|
||||
design -reset
|
||||
read_rtlil <<EOT
|
||||
|
|
@ -177,30 +186,41 @@ end
|
|||
EOT
|
||||
design -save order_test
|
||||
|
||||
# don't rename prematurely (some objects should be named after $name2)
|
||||
# wires are named for being cell outputs
|
||||
logger -expect log "Rename wire .d in top to or_Y" 1
|
||||
logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
|
||||
logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1
|
||||
logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
|
||||
logger -expect log "Renamed 4 objects" 1
|
||||
debug autoname t:$or
|
||||
logger -check-expected
|
||||
|
||||
# $name gets shortest name (otherwise bcd_$__unknown_B)
|
||||
logger -expect log "Rename cell .name in top to a_.__unknown_A" 1
|
||||
# $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A)
|
||||
logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
|
||||
logger -expect log "Renamed 2 objects" 1
|
||||
debug autoname
|
||||
logger -check-expected
|
||||
|
||||
# don't rename prematurely (some objects should be named after $name2)
|
||||
design -load order_test
|
||||
|
||||
# $c gets shortest name, since the cell driving it doesn't have known port
|
||||
# directions (otherwise a_$__unknown_A_Y)
|
||||
logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
|
||||
# $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A)
|
||||
logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
|
||||
logger -expect log "Renamed 6 objects" 1
|
||||
debug autoname
|
||||
logger -check-expected
|
||||
|
||||
# Only selected objects are renamed, but each one gets exactly the name the
|
||||
# unrestricted run above gave it, whatever the selection.
|
||||
design -load order_test
|
||||
logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
|
||||
logger -expect log "Renamed 1 objects" 1
|
||||
debug autoname t:$or
|
||||
logger -check-expected
|
||||
|
||||
design -load order_test
|
||||
logger -expect log "Rename wire .d in top to or_Y" 1
|
||||
logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1
|
||||
logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
|
||||
logger -expect log "Renamed 3 objects" 1
|
||||
debug autoname w:*
|
||||
logger -check-expected
|
||||
|
||||
# $name3 is named after a chain of objects that all keep their $-names
|
||||
design -load order_test
|
||||
logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
|
||||
logger -expect log "Renamed 1 objects" 1
|
||||
debug autoname c:$name3
|
||||
logger -check-expected
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue