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autoname: rewrite
This commit is contained in:
Emil J. Tywoniak
parent
9914b6fa25
commit
fb0bb160ad
2 changed files with 216 additions and 94 deletions
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@ -17,95 +17,233 @@
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*
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*/
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#include "kernel/yosys.h"
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#include <functional>
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#include <queue>
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#include <ranges>
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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typedef struct name_proposal {
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string name;
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// An "object" is a cell or a wire.
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// An object is "private" if its name starts with a '$'.
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//
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// The "autoname" pass renames private objects based on public object names,
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// with suffixes added to show the relationship to the public objects.
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// The pass chooses the "best" names based on minimizing their "cost".
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// The cost of a new name for a private object is the cost along a path
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// to a publicly named object.
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struct cost {
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// score is a property of one "edge", not of the entire path.
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// 0 if the neighbour drives the object, and the wire's fanout otherwise
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unsigned int score = UINT_MAX;
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// New name length
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size_t length = SIZE_MAX;
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// Earlier discovered connection wins
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int edge_pos = 0;
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auto operator<=>(const cost &) const = default;
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};
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// Endpoints of an "edge" are always a cell index and a wire index. Goofy, I know.
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// SigSig connections (module->connections()) don't count
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// as neighbors. This means that the equivalent of `assign $w1 = \w2;` won't lead
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// to $w1 being renamed.
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struct Edge {
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// Cell port name at which the wire connects to the cell
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IdString port;
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int cell;
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int wire;
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bool cell_is_output;
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unsigned int score;
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name_proposal() : name(""), score(-1) { }
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name_proposal(string name, unsigned int score) : name(name), score(score) { }
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bool operator<(const name_proposal &other) const {
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if (score != other.score)
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return score < other.score;
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else
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return name.length() < other.name.length();
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}
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} name_proposal;
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// Edge's position in the edge list
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int pos_in_cell;
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int pos_in_wire;
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};
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int autoname_worker(Module *module, const dict<Wire*, unsigned int>& wire_score)
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// decide() finds shortest names for every object reachable from a public name,
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// cheapest-first. It doesn't apply the renames to the objects yet.
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//
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// commit() then renames in decide() order, which is topological, so a source
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// neighbour always already carries its final uniquify()d name.
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// A selected cell or wire
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struct node {
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// Exactly one of cell/wire is set
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Cell *cell = nullptr;
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Wire *wire = nullptr;
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vector<Edge> edges;
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// Ignores module->connections() just as the rest of the code
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unsigned int fanout = 0;
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bool is_public = false;
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bool renameable = false;
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size_t name_length = 0;
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// Node index from which we want to construct the rename
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int from_node = -1;
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// Cost for the edge from that node
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cost c;
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// Suffix to append to the name of that node
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string suffix;
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// Is this name final?
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bool decided = false;
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};
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// Decides the order of exploring neighbors
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struct queue_item {
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unsigned int score;
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size_t length;
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int index;
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auto operator<=>(const queue_item &) const = default;
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};
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struct ModuleAutonamer
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{
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dict<Cell*, name_proposal> proposed_cell_names;
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dict<Wire*, name_proposal> proposed_wire_names;
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name_proposal best_name;
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Module *module;
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for (auto cell : module->selected_cells()) {
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if (cell->name[0] == '$') {
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// Cells in module order, then wires in the order that they're seen from cells.
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// The index doubles as the tie-break between equally good
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// proposals for different nodes.
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vector<node> nodes;
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vector<int> decided;
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std::priority_queue<queue_item, std::vector<queue_item>, std::greater<>> queue;
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int renamed = 0;
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ModuleAutonamer(Module *module) : module(module) { build_adjacency(); }
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void build_adjacency()
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{
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auto selected = module->selected_cells();
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// Arbitrary. Kinda just for passing tests without modifying them.
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for (auto cell : selected | std::views::reverse)
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nodes.emplace_back().cell = cell;
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int ncells = GetSize(nodes);
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idict<Wire*> wire_ids;
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for (int ci = 0; ci < ncells; ci++) {
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Cell *cell = nodes[ci].cell;
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for (auto &conn : cell->connections()) {
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string suffix;
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for (auto bit : conn.second)
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if (bit.wire != nullptr && bit.wire->name[0] != '$') {
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if (suffix.empty())
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suffix = stringf("_%s_%s", cell->type.unescape(), conn.first.unescape());
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name_proposal proposed_name(
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bit.wire->name.str() + suffix,
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cell->output(conn.first) ? 0 : wire_score.at(bit.wire)
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);
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if (!proposed_cell_names.count(cell) || proposed_name < proposed_cell_names.at(cell)) {
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if (proposed_name < best_name)
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best_name = proposed_name;
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proposed_cell_names[cell] = proposed_name;
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}
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}
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}
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} else {
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for (auto &conn : cell->connections()) {
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string suffix;
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for (auto bit : conn.second)
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if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) {
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if (suffix.empty())
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suffix = stringf("_%s", conn.first.unescape());
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name_proposal proposed_name(
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cell->name.str() + suffix,
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cell->output(conn.first) ? 0 : wire_score.at(bit.wire)
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);
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if (!proposed_wire_names.count(bit.wire) || proposed_name < proposed_wire_names.at(bit.wire)) {
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if (proposed_name < best_name)
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best_name = proposed_name;
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proposed_wire_names[bit.wire] = proposed_name;
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}
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}
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bool cell_is_output = cell->output(conn.first);
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pool<Wire*> seen_in_this_port;
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for (auto bit : conn.second) {
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if (bit.wire == nullptr)
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continue;
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int wi = ncells + wire_ids(bit.wire);
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if (wi == GetSize(nodes))
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nodes.emplace_back().wire = bit.wire;
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nodes[wi].fanout++;
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if (!seen_in_this_port.insert(bit.wire).second)
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continue;
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Edge edge{
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.port = conn.first,
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.cell = ci,
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.wire = wi,
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.cell_is_output = cell_is_output,
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.score = 0, // no fanouts are final yet
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.pos_in_cell = GetSize(nodes[ci].edges),
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.pos_in_wire = GetSize(nodes[wi].edges),
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};
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nodes[ci].edges.push_back(edge);
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nodes[wi].edges.push_back(edge);
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}
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}
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}
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for (auto &nd : nodes) {
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IdString name = nd.cell ? nd.cell->name : nd.wire->name;
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nd.is_public = (name[0] != '$');
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nd.renameable = !nd.is_public && (nd.cell || nd.wire->port_id == 0);
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if (nd.is_public)
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nd.name_length = name.str().size();
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}
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// Only possible once every fanout is known.
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for (auto &nd : nodes)
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for (auto &edge : nd.edges)
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edge.score = edge.cell_is_output ? 0 : nodes[edge.wire].fanout;
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}
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void offer(int from, int n, const Edge &edge, int edge_pos)
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{
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node &nd = nodes[n];
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if (!nd.renameable || nd.decided)
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return;
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string suffix = nd.cell
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? stringf("_%s_%s", nd.cell->type.unescape(), edge.port.unescape())
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: stringf("_%s", edge.port.unescape());
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cost c{edge.score, nodes[from].name_length + suffix.length(), edge_pos};
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if (c >= nd.c)
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return;
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nd.c = c;
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nd.from_node = from;
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nd.name_length = c.length;
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nd.suffix = std::move(suffix);
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queue.push(queue_item{c.score, c.length, n});
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}
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// Expand a public (or newly decided) node. The name it lends
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// is already settled and the neighbour can keep what offer() built
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void expand(int n)
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{
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const node &nd = nodes[n];
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for (auto &edge : nd.edges)
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if (nd.cell)
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offer(n, edge.wire, edge, edge.pos_in_wire);
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else
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offer(n, edge.cell, edge, edge.pos_in_cell);
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}
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void decide()
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{
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for (int n = 0; n < GetSize(nodes); n++)
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if (nodes[n].is_public)
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expand(n);
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while (!queue.empty()) {
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int n = queue.top().index;
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queue.pop();
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if (nodes[n].decided)
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continue;
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nodes[n].decided = true;
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decided.push_back(n);
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expand(n);
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}
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}
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int count = 0;
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// compare against double best score for following comparisons so we don't
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// pre-empt a future iteration
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best_name.score *= 2;
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for (auto &it : proposed_cell_names) {
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if (best_name < it.second)
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continue;
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IdString n = module->uniquify(IdString(it.second.name));
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log_debug("Rename cell %s in %s to %s.\n", it.first, module, n.unescape());
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module->rename(it.first, n);
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count++;
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// The source neighbour is decided before this node, so commit() reaches it
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// first and its name is already final -- uniquify() suffix and all.
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void commit(int n)
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{
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node &nd = nodes[n];
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const node &src = nodes[nd.from_node];
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string full;
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full.reserve(nd.name_length);
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(src.cell ? src.cell->name : src.wire->name).append_to(&full);
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full += nd.suffix;
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IdString name = module->uniquify(IdString(full));
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if (nd.cell) {
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log_debug("Rename cell %s in %s to %s.\n", nd.cell, module, name.unescape());
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module->rename(nd.cell, name);
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} else {
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log_debug("Rename wire %s in %s to %s.\n", nd.wire, module, name.unescape());
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module->rename(nd.wire, name);
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}
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renamed++;
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}
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for (auto &it : proposed_wire_names) {
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if (best_name < it.second)
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continue;
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IdString n = module->uniquify(IdString(it.second.name));
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log_debug("Rename wire %s in %s to %s.\n", it.first, module, n.unescape());
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module->rename(it.first, n);
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count++;
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void run()
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{
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decide();
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for (int n : decided)
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commit(n);
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if (renamed > 0)
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log("Renamed %d objects in module %s.\n", renamed, module);
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}
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return count;
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}
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};
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struct AutonamePass : public Pass {
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AutonamePass() : Pass("autoname", "automatically assign names to objects") { }
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@ -135,24 +273,7 @@ struct AutonamePass : public Pass {
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log_header(design, "Executing AUTONAME pass.\n");
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for (auto module : design->selected_modules())
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{
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dict<Wire*, unsigned int> wire_score;
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for (auto cell : module->selected_cells())
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for (auto &conn : cell->connections())
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for (auto bit : conn.second)
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if (bit.wire != nullptr)
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wire_score[bit.wire]++;
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int count = 0, iter = 0;
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while (1) {
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iter++;
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int n = autoname_worker(module, wire_score);
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if (!n) break;
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count += n;
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}
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if (count > 0)
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log("Renamed %d objects in module %s (%d iterations).\n", count, module, iter);
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}
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ModuleAutonamer(module).run();
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}
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} AutonamePass;
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@ -180,15 +180,16 @@ design -save order_test
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# wires are named for being cell outputs
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logger -expect log "Rename wire .d in top to or_Y" 1
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logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1
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logger -expect log "Renamed 2 objects" 1
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logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1
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logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1
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logger -expect log "Renamed 4 objects" 1
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debug autoname t:$or
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logger -check-expected
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# $name gets shortest name (otherwise bcd_$__unknown_B)
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logger -expect log "Rename cell .name in top to a_.__unknown_A" 1
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# another output wire
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logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1
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logger -expect log "Renamed 4 objects" 1
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logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1
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logger -expect log "Renamed 2 objects" 1
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debug autoname
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logger -check-expected
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