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opt_merge to discard \init of '$' cells with 'Q' port when merging
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d86d073ad6
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@ -323,6 +323,17 @@ struct OptMergeWorker
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log_signal(it.second), log_signal(other_sig));
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log_signal(it.second), log_signal(other_sig));
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module->connect(RTLIL::SigSig(it.second, other_sig));
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module->connect(RTLIL::SigSig(it.second, other_sig));
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assign_map.add(it.second, other_sig);
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assign_map.add(it.second, other_sig);
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if (cell->type.begins_with("$") && it.first == ID(Q)) {
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for (auto c : it.second.chunks()) {
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auto jt = c.wire->attributes.find(ID(init));
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if (jt == c.wire->attributes.end())
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continue;
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for (int i = c.offset; i < c.offset + c.width; i++)
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jt->second[i] = State::Sx;
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}
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dff_init_map.add(it.second, Const(State::Sx, GetSize(it.second)));
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}
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}
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}
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}
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}
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log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
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log_debug(" Removing %s cell `%s' from module `%s'.\n", cell->type.c_str(), cell->name.c_str(), module->name.c_str());
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