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Just don't sort

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This commit is contained in:
Emil J. Tywoniak 2025-09-18 20:56:25 +02:00
parent 9570b39519
commit 8371adf6b5
9 changed files with 2 additions and 10 deletions
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1
backends/blif/blif.cc
View file

@ -653,7 +653,6 @@ struct BlifBackend : public Backend {
std::vector<RTLIL::Module*> mod_list;
design->sort();
for (auto module : design->modules())
{
if (module->get_blackbox_attribute() && !config.blackbox_mode)

1
backends/jny/jny.cc
View file

@ -121,7 +121,6 @@ struct JnyWriter
{
log_assert(design != nullptr);
design->sort();
f << "{\n";
f << " \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\",\n";

1
backends/json/json.cc
View file

@ -288,7 +288,6 @@ struct JsonWriter
void write_design(Design *design_)
{
design = design_;
design->sort();
f << stringf("{\n");
f << stringf(" \"creator\": %s,\n", get_string(yosys_maybe_version()));

1
backends/table/table.cc
View file

@ -63,7 +63,6 @@ struct TableBackend : public Backend {
}
extra_args(f, filename, args, argidx);
design->sort();
for (auto module : design->modules())
{

2
backends/verilog/verilog_backend.cc
View file

@ -2672,7 +2672,7 @@ struct VerilogBackend : public Backend {
Pass::call(design, "clean_zerowidth");
log_pop();
design->sort_modules();
// design->sort_modules();
*f << stringf("/* Generated by %s */\n", yosys_maybe_version());

1
passes/opt/opt.cc
View file

@ -193,7 +193,6 @@ struct OptPass : public Pass {
}
design->optimize();
design->sort();
design->check();
log_header(design, "Finished fast OPT passes.%s\n", fast_mode ? "" : " (There is nothing left to do.)");

2
passes/opt/opt_clean.cc
View file

@ -715,7 +715,6 @@ struct OptCleanPass : public Pass {
log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
design->optimize();
design->sort();
design->check();
keep_cache.reset();
@ -778,7 +777,6 @@ struct CleanPass : public Pass {
log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
design->optimize();
design->sort();
design->check();
keep_cache.reset();

1
techlibs/ice40/ice40_opt.cc
View file

@ -257,7 +257,6 @@ struct Ice40OptPass : public Pass {
}
design->optimize();
design->sort();
design->check();
log_header(design, "Finished OPT passes. (There is nothing left to do.)\n");

2
tests/arch/xilinx/dsp_cascade.ys
View file

@ -39,7 +39,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
design -load postopt
cd cascade
select -assert-count 3 t:DSP48A1
select -assert-count 5 t:FDRE # No cascade for A input
select -assert-count 10 t:FDRE # No cascade for A input
select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D
# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
# (see above for explanation)