diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index ab7861802..7fbb94244 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -653,7 +653,6 @@ struct BlifBackend : public Backend {
 
 		std::vector<RTLIL::Module*> mod_list;
 
-		design->sort();
 		for (auto module : design->modules())
 		{
 			if (module->get_blackbox_attribute() && !config.blackbox_mode)
diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc
index ee0c0d14c..63834df8e 100644
--- a/backends/jny/jny.cc
+++ b/backends/jny/jny.cc
@@ -121,7 +121,6 @@ struct JnyWriter
     {
         log_assert(design != nullptr);
 
-        design->sort();
 
         f << "{\n";
         f << "  \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\",\n";
diff --git a/backends/json/json.cc b/backends/json/json.cc
index b04083622..1cbf3fc0a 100644
--- a/backends/json/json.cc
+++ b/backends/json/json.cc
@@ -288,7 +288,6 @@ struct JsonWriter
 	void write_design(Design *design_)
 	{
 		design = design_;
-		design->sort();
 
 		f << stringf("{\n");
 		f << stringf("  \"creator\": %s,\n", get_string(yosys_maybe_version()));
diff --git a/backends/table/table.cc b/backends/table/table.cc
index 2bf64e7b1..b1218b5d6 100644
--- a/backends/table/table.cc
+++ b/backends/table/table.cc
@@ -63,7 +63,6 @@ struct TableBackend : public Backend {
 		}
 		extra_args(f, filename, args, argidx);
 
-		design->sort();
 
 		for (auto module : design->modules())
 		{
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index c747aa901..1d1cefdc7 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -2672,7 +2672,7 @@ struct VerilogBackend : public Backend {
 		Pass::call(design, "clean_zerowidth");
 		log_pop();
 
-               design->sort_modules();
+		// design->sort_modules();
 
 		*f << stringf("/* Generated by %s */\n", yosys_maybe_version());
 
diff --git a/passes/opt/opt.cc b/passes/opt/opt.cc
index ec5760cd9..983437e64 100644
--- a/passes/opt/opt.cc
+++ b/passes/opt/opt.cc
@@ -193,7 +193,6 @@ struct OptPass : public Pass {
 		}
 
 		design->optimize();
-		design->sort();
 		design->check();
 
 		log_header(design, "Finished fast OPT passes.%s\n", fast_mode ? "" : " (There is nothing left to do.)");
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 996a9b3c9..990469240 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -715,7 +715,6 @@ struct OptCleanPass : public Pass {
 			log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
 
 		design->optimize();
-		design->sort();
 		design->check();
 
 		keep_cache.reset();
@@ -778,7 +777,6 @@ struct CleanPass : public Pass {
 			log("Removed %d unused cells and %d unused wires.\n", count_rm_cells, count_rm_wires);
 
 		design->optimize();
-		design->sort();
 		design->check();
 
 		keep_cache.reset();
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc
index b13d33018..cf6c4ec77 100644
--- a/techlibs/ice40/ice40_opt.cc
+++ b/techlibs/ice40/ice40_opt.cc
@@ -257,7 +257,6 @@ struct Ice40OptPass : public Pass {
 		}
 
 		design->optimize();
-		design->sort();
 		design->check();
 
 		log_header(design, "Finished OPT passes. (There is nothing left to do.)\n");
diff --git a/tests/arch/xilinx/dsp_cascade.ys b/tests/arch/xilinx/dsp_cascade.ys
index ca6b619b9..73f0e77a6 100644
--- a/tests/arch/xilinx/dsp_cascade.ys
+++ b/tests/arch/xilinx/dsp_cascade.ys
@@ -39,7 +39,7 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
 design -load postopt
 cd cascade
 select -assert-count 3 t:DSP48A1
-select -assert-count 5 t:FDRE # No cascade for A input
+select -assert-count 10 t:FDRE # No cascade for A input
 select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D
 # Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
 #   (see above for explanation)