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verific: import attributes on ports

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Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
This commit is contained in:
N. Engelhardt 2023-10-20 18:31:41 +02:00
parent 1b6d1e9419
commit 833b67af80
3 changed files with 10 additions and 5 deletions
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7
frontends/verific/verific.cc
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@ -1345,7 +1345,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex()); wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
wire->upto = portbus->IsUp(); wire->upto = portbus->IsUp();
import_attributes(wire->attributes, portbus, nl); import_attributes(wire->attributes, portbus, nl);
SetIter si ;
Port *port ;
FOREACH_PORT_OF_PORTBUS(portbus, si, port) {
import_attributes(wire->attributes, port->GetNet(), nl);
break;
}
bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN; bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN;
if (portbus_input) if (portbus_input)
wire->port_input = true; wire->port_input = true;

4
tests/verific/memory_semantics.ys
View file

@ -26,9 +26,9 @@ reg [DEPTH_LOG2-1:0] counter = 0;
reg done = 1'b0; reg done = 1'b0;
always @(posedge clk) begin always @(posedge clk) begin
if (!done) if (!done)
counter = counter + 1; counter = counter + 1'b1;
if (counter == 0) if (counter == 0)
done = 1; done = 1'b1;
end end
wire [WIDTH-1:0] old_data = PRIME1 * counter; wire [WIDTH-1:0] old_data = PRIME1 * counter;

4
tests/verific/rom_case.ys
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@ -30,7 +30,7 @@ select -assert-count 1 t:RAM_BLOCK_SDP
design -reset design -reset
verific -vhdl << verific -vhdl <<EOF
library IEEE; library IEEE;
use IEEE.std_logic_1164.all; use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;
@ -66,7 +66,7 @@ begin
end architecture rtl; end architecture rtl;
EOF EOF
hierarchy -top rom hierarchy -top rom_example
proc proc
opt opt
opt -full opt -full