From 833b67af80a748b7c1f8a775c5721b2815151f34 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Fri, 20 Oct 2023 18:31:41 +0200 Subject: [PATCH] verific: import attributes on ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Miodrag Milanović --- frontends/verific/verific.cc | 7 ++++++- tests/verific/memory_semantics.ys | 4 ++-- tests/verific/rom_case.ys | 4 ++-- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 115a42e33..5ac8f8b39 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1345,7 +1345,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex()); wire->upto = portbus->IsUp(); import_attributes(wire->attributes, portbus, nl); - + SetIter si ; + Port *port ; + FOREACH_PORT_OF_PORTBUS(portbus, si, port) { + import_attributes(wire->attributes, port->GetNet(), nl); + break; + } bool portbus_input = portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN; if (portbus_input) wire->port_input = true; diff --git a/tests/verific/memory_semantics.ys b/tests/verific/memory_semantics.ys index 92f4fd2dc..adcd3a4ca 100644 --- a/tests/verific/memory_semantics.ys +++ b/tests/verific/memory_semantics.ys @@ -26,9 +26,9 @@ reg [DEPTH_LOG2-1:0] counter = 0; reg done = 1'b0; always @(posedge clk) begin if (!done) - counter = counter + 1; + counter = counter + 1'b1; if (counter == 0) - done = 1; + done = 1'b1; end wire [WIDTH-1:0] old_data = PRIME1 * counter; diff --git a/tests/verific/rom_case.ys b/tests/verific/rom_case.ys index 171c16db7..253cc0766 100644 --- a/tests/verific/rom_case.ys +++ b/tests/verific/rom_case.ys @@ -30,7 +30,7 @@ select -assert-count 1 t:RAM_BLOCK_SDP design -reset -verific -vhdl << +verific -vhdl <