mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-30 01:07:14 +00:00
Code Activity

verific: import attributes on ports

Browse source 
Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
This commit is contained in:
N. Engelhardt 2023-10-20 18:31:41 +02:00
parent 1b6d1e9419
commit 833b67af80
3 changed files with 10 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

4
tests/verific/rom_case.ys
View file

@ -30,7 +30,7 @@ select -assert-count 1 t:RAM_BLOCK_SDP
design -reset
verific -vhdl <<
verific -vhdl <<EOF
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
@ -66,7 +66,7 @@ begin
end architecture rtl;
EOF
hierarchy -top rom
hierarchy -top rom_example
proc
opt
opt -full