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Docs: Fix Verific builds table formatting

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PDF don't like the long headers, so instead use placeholders a-d with elaborations below.
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Krystine Sherwin 2024-08-22 10:03:59 +12:00
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docs/source/yosys_internals/extending_yosys/build_verific.rst
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@ -110,23 +110,29 @@ lists a series of build configurations which are possible, but only provide a
limited subset of features. Please note that support is limited without YosysHQ limited subset of features. Please note that support is limited without YosysHQ
specific extensions of Verific library. specific extensions of Verific library.
+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ +--------------------------------------------------------------------------+---+---+---+-----------+
| | Configuration values beginning with ENABLE_VERIFIC\_ | | | Configuration values |
+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ +--------------------------------------------------------------------------+-----+-----+-----+-----+
| Features | SYSTEMVERILOG | VHDL | HIER_TREE | YOSYSHQ_EXTENSIONS | | Features | a | b | c | d |
+==========================================================================+===============+======+===========+====================+ +==========================================================================+=====+=====+=====+=====+
| SystemVerilog + RTL elaboration | 1 | 0 | 0 | 0 | | SystemVerilog + RTL elaboration | 1 | 0 | 0 | 0 |
+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ +--------------------------------------------------------------------------+-----+-----+-----+-----+
| VHDL + RTL elaboration | 0 | 1 | 0 | 0 | | VHDL + RTL elaboration | 0 | 1 | 0 | 0 |
+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ +--------------------------------------------------------------------------+-----+-----+-----+-----+
| SystemVerilog + VHDL + RTL elaboration | 1 | 1 | 0 | 0 | | SystemVerilog + VHDL + RTL elaboration | 1 | 1 | 0 | 0 |
+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ +--------------------------------------------------------------------------+-----+-----+-----+-----+
| SystemVerilog + RTL elaboration + Static elaboration + Hier tree | 1 | 0 | 1 | 0 | | SystemVerilog + RTL elaboration + Static elaboration + Hier tree | 1 | 0 | 1 | 0 |
+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ +--------------------------------------------------------------------------+-----+-----+-----+-----+
| VHDL + RTL elaboration + Static elaboration + Hier tree | 0 | 1 | 1 | 0 | | VHDL + RTL elaboration + Static elaboration + Hier tree | 0 | 1 | 1 | 0 |
+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ +--------------------------------------------------------------------------+-----+-----+-----+-----+
| SystemVerilog + VHDL + RTL elaboration + Static elaboration + Hier tree | 1 | 1 | 1 | 0 | | SystemVerilog + VHDL + RTL elaboration + Static elaboration + Hier tree | 1 | 1 | 1 | 0 |
+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ +--------------------------------------------------------------------------+-----+-----+-----+-----+
Configuration values:
a. ``ENABLE_VERIFIC_SYSTEMVERILOG``
b. ``ENABLE_VERIFIC_VHDL``
c. ``ENABLE_VERIFIC_HIER_TREE``
d. ``ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS``
.. note:: .. note::