From 8145461c7898754985595f84787f4058e0c9aa8d Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 22 Aug 2024 10:03:59 +1200 Subject: [PATCH] Docs: Fix Verific builds table formatting PDF don't like the long headers, so instead use placeholders a-d with elaborations below. --- .../extending_yosys/build_verific.rst | 40 +++++++++++-------- 1 file changed, 23 insertions(+), 17 deletions(-) diff --git a/docs/source/yosys_internals/extending_yosys/build_verific.rst b/docs/source/yosys_internals/extending_yosys/build_verific.rst index 16ec53645..ae453886f 100644 --- a/docs/source/yosys_internals/extending_yosys/build_verific.rst +++ b/docs/source/yosys_internals/extending_yosys/build_verific.rst @@ -110,23 +110,29 @@ lists a series of build configurations which are possible, but only provide a limited subset of features. Please note that support is limited without YosysHQ specific extensions of Verific library. -+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ -| | Configuration values beginning with ENABLE_VERIFIC\_ | -+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ -| Features | SYSTEMVERILOG | VHDL | HIER_TREE | YOSYSHQ_EXTENSIONS | -+==========================================================================+===============+======+===========+====================+ -| SystemVerilog + RTL elaboration | 1 | 0 | 0 | 0 | -+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ -| VHDL + RTL elaboration | 0 | 1 | 0 | 0 | -+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ -| SystemVerilog + VHDL + RTL elaboration | 1 | 1 | 0 | 0 | -+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ -| SystemVerilog + RTL elaboration + Static elaboration + Hier tree | 1 | 0 | 1 | 0 | -+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ -| VHDL + RTL elaboration + Static elaboration + Hier tree | 0 | 1 | 1 | 0 | -+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ -| SystemVerilog + VHDL + RTL elaboration + Static elaboration + Hier tree | 1 | 1 | 1 | 0 | -+--------------------------------------------------------------------------+---------------+------+-----------+--------------------+ ++--------------------------------------------------------------------------+---+---+---+-----------+ +| | Configuration values | ++--------------------------------------------------------------------------+-----+-----+-----+-----+ +| Features | a | b | c | d | ++==========================================================================+=====+=====+=====+=====+ +| SystemVerilog + RTL elaboration | 1 | 0 | 0 | 0 | ++--------------------------------------------------------------------------+-----+-----+-----+-----+ +| VHDL + RTL elaboration | 0 | 1 | 0 | 0 | ++--------------------------------------------------------------------------+-----+-----+-----+-----+ +| SystemVerilog + VHDL + RTL elaboration | 1 | 1 | 0 | 0 | ++--------------------------------------------------------------------------+-----+-----+-----+-----+ +| SystemVerilog + RTL elaboration + Static elaboration + Hier tree | 1 | 0 | 1 | 0 | ++--------------------------------------------------------------------------+-----+-----+-----+-----+ +| VHDL + RTL elaboration + Static elaboration + Hier tree | 0 | 1 | 1 | 0 | ++--------------------------------------------------------------------------+-----+-----+-----+-----+ +| SystemVerilog + VHDL + RTL elaboration + Static elaboration + Hier tree | 1 | 1 | 1 | 0 | ++--------------------------------------------------------------------------+-----+-----+-----+-----+ + +Configuration values: + a. ``ENABLE_VERIFIC_SYSTEMVERILOG`` + b. ``ENABLE_VERIFIC_VHDL`` + c. ``ENABLE_VERIFIC_HIER_TREE`` + d. ``ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS`` .. note::