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continue cleanup of files for intel-le handling

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This commit is contained in:
Artur Swiderski 2020-10-14 00:56:16 +02:00
parent 36bd075865
commit 80c08850c9
10 changed files with 139 additions and 67 deletions
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10
techlibs/intel_le/common/quartus_rename.v
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@ -1,7 +1,7 @@
`ifdef cyclonev
`define LCELL cyclonev_lcell_comb
`define MAC cyclonev_mac
`define MLAB cyclonev_mlab_cell
`ifdef cycloneiv
`define LCELL cycloneiv_lcell_comb
`define MAC cycloneiv_mac
`define MLAB cycloneiv_mlab_cell
`endif
`ifdef cyclone10gx
`define LCELL cyclone10gx_lcell_comb
@ -140,7 +140,7 @@ output [CFG_DBITS-1:0] B1DATA;
// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
// you initialise the RAM cell via hex literals. If they were implemented.
cyclonev_ram_block #(
cycloneiv_ram_block #(
.operation_mode("dual_port"),
.logical_ram_name(_TECHMAP_CELLNAME_),
.port_a_address_width(CFG_ABITS),