From 80c08850c936b44246cff43c4e92bda6eb0878df Mon Sep 17 00:00:00 2001 From: Artur Swiderski Date: Wed, 14 Oct 2020 00:56:16 +0200 Subject: [PATCH] continue cleanup of files for intel-le handling --- techlibs/intel_le/Makefile.inc | 12 ++-- techlibs/intel_le/common/arith_le_map.v | 71 ++++++++++++++++++++++ techlibs/intel_le/common/bram_m9k.txt | 33 ++++++++++ techlibs/intel_le/common/dff_sim.v | 2 +- techlibs/intel_le/common/le_sim.v | 14 ++--- techlibs/intel_le/common/lutram_mlab.txt | 18 ------ techlibs/intel_le/common/megafunction_bb.v | 6 +- techlibs/intel_le/common/quartus_rename.v | 10 +-- techlibs/intel_le/cycloneiv/cells_sim.v | 14 ++--- techlibs/intel_le/synth_intel_le.cc | 26 +++----- 10 files changed, 139 insertions(+), 67 deletions(-) create mode 100644 techlibs/intel_le/common/arith_le_map.v create mode 100644 techlibs/intel_le/common/bram_m9k.txt delete mode 100644 techlibs/intel_le/common/lutram_mlab.txt diff --git a/techlibs/intel_le/Makefile.inc b/techlibs/intel_le/Makefile.inc index efc9de821..5c5260ea3 100644 --- a/techlibs/intel_le/Makefile.inc +++ b/techlibs/intel_le/Makefile.inc @@ -5,22 +5,20 @@ OBJS += techlibs/intel_le/synth_intel_le.o $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/abc9_map.v)) $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/abc9_unmap.v)) $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/abc9_model.v)) -$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/alm_map.v)) -$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/alm_sim.v)) -$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/arith_alm_map.v)) +$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/le_map.v)) +$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/le_sim.v)) +$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/arith_le_map.v)) $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dff_map.v)) $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dff_sim.v)) $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dsp_sim.v)) $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/dsp_map.v)) $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/mem_sim.v)) -$(eval $(call add_share_file,share/intel_le/cyclonev,techlibs/intel_le/cycloneiv/cells_sim.v)) +$(eval $(call add_share_file,share/intel_le/cycloneiv,techlibs/intel_le/cycloneiv/cells_sim.v)) # RAM -$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/bram_m10k.txt)) -$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/bram_m20k.txt)) +$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/bram_m9k.txt)) $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/bram_m20k_map.v)) -$(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/lutram_mlab.txt)) # Miscellaneous $(eval $(call add_share_file,share/intel_le/common,techlibs/intel_le/common/megafunction_bb.v)) diff --git a/techlibs/intel_le/common/arith_le_map.v b/techlibs/intel_le/common/arith_le_map.v new file mode 100644 index 000000000..8515eeb56 --- /dev/null +++ b/techlibs/intel_le/common/arith_le_map.v @@ -0,0 +1,71 @@ +`default_nettype none + +module \$alu (A, B, CI, BI, X, Y, CO); + +parameter A_SIGNED = 0; +parameter B_SIGNED = 0; +parameter A_WIDTH = 1; +parameter B_WIDTH = 1; +parameter Y_WIDTH = 1; + +parameter _TECHMAP_CONSTMSK_CI_ = 0; +parameter _TECHMAP_CONSTVAL_CI_ = 0; + +(* force_downto *) +input [A_WIDTH-1:0] A; +(* force_downto *) +input [B_WIDTH-1:0] B; +input CI, BI; +(* force_downto *) +output [Y_WIDTH-1:0] X, Y, CO; + +(* force_downto *) +wire [Y_WIDTH-1:0] A_buf, B_buf; +\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); +\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + +(* force_downto *) +wire [Y_WIDTH-1:0] AA = A_buf; +(* force_downto *) +wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; +(* force_downto *) +wire [Y_WIDTH-1:0] BX = B_buf; +wire [Y_WIDTH:0] ALM_CARRY; + +// Start of carry chain +generate + if (_TECHMAP_CONSTMSK_CI_ == 1) begin + assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_; + end else begin + MISTRAL_ALUT_ARITH #( + .LUT0(16'b1010_1010_1010_1010), // Q = A + .LUT1(16'b0000_0000_0000_0000), // Q = 0 (LUT1's input to the adder is inverted) + ) alm_start ( + .A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1), + .CI(1'b0), + .CO(ALM_CARRY[0]) + ); + end +endgenerate + +// Carry chain +genvar i; +generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice + // TODO: mwk suggests that a pass could merge pre-adder logic into this. + MISTRAL_ALUT_ARITH #( + .LUT0(16'b1010_1010_1010_1010), // Q = A + .LUT1(16'b1100_0011_1100_0011), // Q = C ? B : ~B (LUT1's input to the adder is inverted) + ) alm_i ( + .A(AA[i]), .B(BX[i]), .C(BI), .D0(1'b1), .D1(1'b1), + .CI(ALM_CARRY[i]), + .SO(Y[i]), + .CO(ALM_CARRY[i+1]) + ); + + // ALM carry chain is not directly accessible, so calculate the carry through soft logic if really needed. + assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i])); +end endgenerate + +assign X = AA ^ BB; + +endmodule diff --git a/techlibs/intel_le/common/bram_m9k.txt b/techlibs/intel_le/common/bram_m9k.txt new file mode 100644 index 000000000..e9355fe2c --- /dev/null +++ b/techlibs/intel_le/common/bram_m9k.txt @@ -0,0 +1,33 @@ +bram MISTRAL_M10K + init 0 # TODO: Re-enable when I figure out how BRAM init works + abits 13 @D8192x1 + dbits 1 @D8192x1 + abits 12 @D4096x2 + dbits 2 @D4096x2 + abits 11 @D2048x4 @D2048x5 + dbits 4 @D2048x4 + dbits 5 @D2048x5 + abits 10 @D1024x8 @D1024x10 + dbits 8 @D1024x8 + dbits 10 @D1024x10 + abits 9 @D512x16 @D512x20 + dbits 16 @D512x16 + dbits 20 @D512x20 + abits 8 @D256x32 @D256x40 + dbits 32 @D256x32 + dbits 40 @D256x40 + groups 2 + ports 1 1 + wrmode 1 0 + # read enable; write enable + byte enables (only for multiples of 8) + enable 1 1 + transp 0 0 + clocks 1 1 + clkpol 1 1 +endbram + + +match MISTRAL_M10K + min efficiency 5 + make_transp +endmatch diff --git a/techlibs/intel_le/common/dff_sim.v b/techlibs/intel_le/common/dff_sim.v index d2cff0adb..05c3dce86 100644 --- a/techlibs/intel_le/common/dff_sim.v +++ b/techlibs/intel_le/common/dff_sim.v @@ -60,7 +60,7 @@ module MISTRAL_FF( output reg Q ); -`ifdef cyclonev +`ifdef cycloneiv specify if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 731; if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 890; diff --git a/techlibs/intel_le/common/le_sim.v b/techlibs/intel_le/common/le_sim.v index 906a95b0b..1cd955362 100644 --- a/techlibs/intel_le/common/le_sim.v +++ b/techlibs/intel_le/common/le_sim.v @@ -82,7 +82,7 @@ module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q); parameter [63:0] LUT = 64'h0000_0000_0000_0000; -`ifdef cyclonev +`ifdef cycloneiv specify (A => Q) = 605; (B => Q) = 583; @@ -113,7 +113,7 @@ module MISTRAL_ALUT5(input A, B, C, D, E, output Q); parameter [31:0] LUT = 32'h0000_0000; -`ifdef cyclonev +`ifdef cycloneiv specify (A => Q) = 583; (B => Q) = 510; @@ -142,7 +142,7 @@ module MISTRAL_ALUT4(input A, B, C, D, output Q); parameter [15:0] LUT = 16'h0000; -`ifdef cyclonev +`ifdef cycloneiv specify (A => Q) = 510; (B => Q) = 512; @@ -169,7 +169,7 @@ module MISTRAL_ALUT3(input A, B, C, output Q); parameter [7:0] LUT = 8'h00; -`ifdef cyclonev +`ifdef cycloneiv specify (A => Q) = 510; (B => Q) = 400; @@ -194,7 +194,7 @@ module MISTRAL_ALUT2(input A, B, output Q); parameter [3:0] LUT = 4'h0; -`ifdef cyclonev +`ifdef cycloneiv specify (A => Q) = 400; (B => Q) = 97; @@ -215,7 +215,7 @@ endmodule (* abc9_lut=1, lib_whitebox *) module MISTRAL_NOT(input A, output Q); -`ifdef cyclonev +`ifdef cycloneiv specify (A => Q) = 97; endspecify @@ -236,7 +236,7 @@ module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, (* abc9_carry *) input CI, outp parameter LUT0 = 16'h0000; parameter LUT1 = 16'h0000; -`ifdef cyclonev +`ifdef cycloneiv specify (A => SO) = 1342; (B => SO) = 1323; diff --git a/techlibs/intel_le/common/lutram_mlab.txt b/techlibs/intel_le/common/lutram_mlab.txt deleted file mode 100644 index 3cc69399d..000000000 --- a/techlibs/intel_le/common/lutram_mlab.txt +++ /dev/null @@ -1,18 +0,0 @@ -bram MISTRAL_MLAB - init 0 # TODO: Re-enable when Yosys remembers the original filename. - abits 5 - dbits 1 - groups 2 - ports 1 1 - wrmode 1 0 - # write enable - enable 1 0 - transp 0 0 - clocks 1 0 - clkpol 1 1 -endbram - -match MISTRAL_MLAB - min efficiency 5 - make_outreg -endmatch \ No newline at end of file diff --git a/techlibs/intel_le/common/megafunction_bb.v b/techlibs/intel_le/common/megafunction_bb.v index 874f293b1..0f723f7a1 100644 --- a/techlibs/intel_le/common/megafunction_bb.v +++ b/techlibs/intel_le/common/megafunction_bb.v @@ -539,7 +539,7 @@ output eccstatus; endmodule (* blackbox *) -module cyclonev_mlab_cell(portaaddr, portadatain, portbaddr, portbdataout, ena0, clk0, clk1); +module cycloneiv_mlab_cell(portaaddr, portadatain, portbaddr, portbdataout, ena0, clk0, clk1); parameter logical_ram_name = ""; parameter logical_ram_depth = 32; @@ -562,7 +562,7 @@ input ena0, clk0, clk1; endmodule (* blackbox *) -module cyclonev_mac(ax, ay, resulta); +module cycloneiv_mac(ax, ay, resulta); parameter ax_width = 9; parameter signed_max = "true"; @@ -594,7 +594,7 @@ output [result_a_width-1:0] resulta; endmodule (* blackbox *) -module cyclonev_ram_block(portaaddr, portadatain, portawe, portbaddr, portbdataout, portbre, clk0); +module cycloneiv_ram_block(portaaddr, portadatain, portawe, portbaddr, portbdataout, portbre, clk0); parameter operation_mode = "dual_port"; parameter logical_ram_name = ""; diff --git a/techlibs/intel_le/common/quartus_rename.v b/techlibs/intel_le/common/quartus_rename.v index 3b4628675..047f833f8 100644 --- a/techlibs/intel_le/common/quartus_rename.v +++ b/techlibs/intel_le/common/quartus_rename.v @@ -1,7 +1,7 @@ -`ifdef cyclonev -`define LCELL cyclonev_lcell_comb -`define MAC cyclonev_mac -`define MLAB cyclonev_mlab_cell +`ifdef cycloneiv +`define LCELL cycloneiv_lcell_comb +`define MAC cycloneiv_mac +`define MLAB cycloneiv_mlab_cell `endif `ifdef cyclone10gx `define LCELL cyclone10gx_lcell_comb @@ -140,7 +140,7 @@ output [CFG_DBITS-1:0] B1DATA; // Much like the MLAB, the M10K has mem_init[01234] parameters which would let // you initialise the RAM cell via hex literals. If they were implemented. -cyclonev_ram_block #( +cycloneiv_ram_block #( .operation_mode("dual_port"), .logical_ram_name(_TECHMAP_CELLNAME_), .port_a_address_width(CFG_ABITS), diff --git a/techlibs/intel_le/cycloneiv/cells_sim.v b/techlibs/intel_le/cycloneiv/cells_sim.v index f7abfaf14..60824ef03 100644 --- a/techlibs/intel_le/cycloneiv/cells_sim.v +++ b/techlibs/intel_le/cycloneiv/cells_sim.v @@ -25,21 +25,21 @@ module GND (output G); endmodule // GND /* Altera Cyclone IV devices Input Buffer Primitive */ -module cyclonev_io_ibuf +module cycloneiv_io_ibuf (output o, input i, input ibar); assign ibar = ibar; assign o = i; -endmodule // cyclonev_io_ibuf +endmodule // cycloneiv_io_ibuf /* Altera Cyclone IV devices Output Buffer Primitive */ -module cyclonev_io_obuf +module cycloneiv_io_obuf (output o, input i, input oe); assign o = i; assign oe = oe; -endmodule // cyclonev_io_obuf +endmodule // cycloneiv_io_obuf /* Altera Cyclone V LUT Primitive */ -module cyclonev_lcell_comb +module cycloneiv_lcell_comb (output combout, cout, sumout, shareout, input dataa, datab, datac, datad, input datae, dataf, datag, cin, @@ -47,7 +47,7 @@ module cyclonev_lcell_comb parameter lut_mask = 64'hFFFFFFFFFFFFFFFF; parameter dont_touch = "off"; - parameter lpm_type = "cyclonev_lcell_comb"; + parameter lpm_type = "cycloneiv_lcell_comb"; parameter shared_arith = "off"; parameter extended_lut = "off"; @@ -121,7 +121,7 @@ module cyclonev_lcell_comb initial $display("Advanced ALM lut combine is not implemented yet"); `endif `endif -endmodule // cyclonev_lcell_comb +endmodule // cycloneiv_lcell_comb /* Altera D Flip-Flop Primitive */ diff --git a/techlibs/intel_le/synth_intel_le.cc b/techlibs/intel_le/synth_intel_le.cc index 8c65c43fa..910eed4ad 100644 --- a/techlibs/intel_le/synth_intel_le.cc +++ b/techlibs/intel_le/synth_intel_le.cc @@ -62,9 +62,6 @@ struct SynthIntelLEPass : public ScriptPass { log(" from label is synonymous to 'begin', and empty to label is\n"); log(" synonymous to the end of the command list.\n"); log("\n"); - log(" -nolutram\n"); - log(" do not use LUT RAM cells in output netlist\n"); - log("\n"); log(" -nobram\n"); log(" do not use block RAM cells in output netlist\n"); log("\n"); @@ -77,17 +74,16 @@ struct SynthIntelLEPass : public ScriptPass { } string top_opt, family_opt, bram_type, vout_file; - bool flatten, quartus, nolutram, nobram, dff, nodsp; + bool flatten, quartus, nobram, dff, nodsp; void clear_flags() override { top_opt = "-auto-top"; family_opt = "cycloneiv"; - bram_type = "m10k"; + bram_type = "m9k"; vout_file = ""; flatten = true; quartus = false; - nolutram = false; nobram = false; dff = false; nodsp = false; @@ -125,10 +121,6 @@ struct SynthIntelLEPass : public ScriptPass { quartus = true; continue; } - if (args[argidx] == "-nolutram") { - nolutram = true; - continue; - } if (args[argidx] == "-nobram") { nobram = true; continue; @@ -174,9 +166,9 @@ struct SynthIntelLEPass : public ScriptPass { } if (check_label("begin")) { - if (family_opt == "cyclonev") + if (family_opt == "cycloneiv") run(stringf("read_verilog -sv -lib +/intel_le/%s/cells_sim.v", family_opt.c_str())); - run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/alm_sim.v", family_opt.c_str())); + run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/le_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/dff_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/dsp_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_le/common/mem_sim.v", family_opt.c_str())); @@ -204,11 +196,11 @@ struct SynthIntelLEPass : public ScriptPass { run("peepopt"); run("opt_clean"); run("share"); - run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); + run("techmap -map +/cmp2lut.v -D LUT_WIDTH=6"); run("opt_expr"); run("opt_clean"); run("alumacc"); - run("techmap -map +/intel_le/common/arith_alm_map.v -map +/intel_le/common/dsp_map.v"); + run("techmap -map +/intel_le/common/arith_le_map.v -map +/intel_le/common/dsp_map.v"); run("opt"); run("memory -nomap"); run("opt_clean"); @@ -220,10 +212,6 @@ struct SynthIntelLEPass : public ScriptPass { run(stringf("techmap -map +/intel_le/common/bram_%s_map.v", bram_type.c_str())); } - if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) { - run("memory_bram -rules +/intel_le/common/lutram_mlab.txt", "(for Cyclone IV )"); - } - if (check_label("map_ffram")) { run("memory_map"); run("opt -full"); @@ -241,7 +229,7 @@ struct SynthIntelLEPass : public ScriptPass { run("techmap -map +/intel_le/common/abc9_map.v"); run(stringf("abc9 %s -maxlut 6 -W 600", help_mode ? "[-dff]" : dff ? "-dff" : "")); run("techmap -map +/intel_le/common/abc9_unmap.v"); - run("techmap -map +/intel_le/common/alm_map.v"); + run("techmap -map +/intel_le/common/le_map.v"); run("opt -fast"); run("autoname"); run("clean");