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continue cleanup of files for intel-le handling
This commit is contained in:
Artur Swiderski
parent
36bd075865
commit
80c08850c9
10 changed files with 139 additions and 67 deletions
71
techlibs/intel_le/common/arith_le_map.v
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71
techlibs/intel_le/common/arith_le_map.v
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@ -0,0 +1,71 @@
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`default_nettype none
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module \$alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 1;
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parameter B_WIDTH = 1;
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parameter Y_WIDTH = 1;
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parameter _TECHMAP_CONSTMSK_CI_ = 0;
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parameter _TECHMAP_CONSTVAL_CI_ = 0;
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(* force_downto *)
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input [A_WIDTH-1:0] A;
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(* force_downto *)
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input [B_WIDTH-1:0] B;
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input CI, BI;
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(* force_downto *)
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output [Y_WIDTH-1:0] X, Y, CO;
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(* force_downto *)
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wire [Y_WIDTH-1:0] A_buf, B_buf;
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\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
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\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
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(* force_downto *)
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wire [Y_WIDTH-1:0] AA = A_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
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(* force_downto *)
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wire [Y_WIDTH-1:0] BX = B_buf;
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wire [Y_WIDTH:0] ALM_CARRY;
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// Start of carry chain
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generate
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if (_TECHMAP_CONSTMSK_CI_ == 1) begin
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assign ALM_CARRY[0] = _TECHMAP_CONSTVAL_CI_;
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end else begin
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MISTRAL_ALUT_ARITH #(
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.LUT0(16'b1010_1010_1010_1010), // Q = A
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.LUT1(16'b0000_0000_0000_0000), // Q = 0 (LUT1's input to the adder is inverted)
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) alm_start (
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.A(CI), .B(1'b1), .C(1'b1), .D0(1'b1), .D1(1'b1),
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.CI(1'b0),
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.CO(ALM_CARRY[0])
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);
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end
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endgenerate
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// Carry chain
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genvar i;
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generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice
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// TODO: mwk suggests that a pass could merge pre-adder logic into this.
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MISTRAL_ALUT_ARITH #(
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.LUT0(16'b1010_1010_1010_1010), // Q = A
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.LUT1(16'b1100_0011_1100_0011), // Q = C ? B : ~B (LUT1's input to the adder is inverted)
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) alm_i (
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.A(AA[i]), .B(BX[i]), .C(BI), .D0(1'b1), .D1(1'b1),
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.CI(ALM_CARRY[i]),
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.SO(Y[i]),
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.CO(ALM_CARRY[i+1])
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);
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// ALM carry chain is not directly accessible, so calculate the carry through soft logic if really needed.
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assign CO[i] = (AA[i] && BB[i]) || ((Y[i] ^ AA[i] ^ BB[i]) && (AA[i] || BB[i]));
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end endgenerate
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assign X = AA ^ BB;
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endmodule
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33
techlibs/intel_le/common/bram_m9k.txt
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33
techlibs/intel_le/common/bram_m9k.txt
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@ -0,0 +1,33 @@
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bram MISTRAL_M10K
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init 0 # TODO: Re-enable when I figure out how BRAM init works
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abits 13 @D8192x1
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dbits 1 @D8192x1
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abits 12 @D4096x2
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dbits 2 @D4096x2
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abits 11 @D2048x4 @D2048x5
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dbits 4 @D2048x4
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dbits 5 @D2048x5
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abits 10 @D1024x8 @D1024x10
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dbits 8 @D1024x8
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dbits 10 @D1024x10
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abits 9 @D512x16 @D512x20
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dbits 16 @D512x16
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dbits 20 @D512x20
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abits 8 @D256x32 @D256x40
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dbits 32 @D256x32
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dbits 40 @D256x40
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groups 2
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ports 1 1
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wrmode 1 0
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# read enable; write enable + byte enables (only for multiples of 8)
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enable 1 1
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transp 0 0
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clocks 1 1
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clkpol 1 1
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endbram
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match MISTRAL_M10K
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min efficiency 5
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make_transp
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endmatch
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@ -60,7 +60,7 @@ module MISTRAL_FF(
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output reg Q
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);
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`ifdef cyclonev
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`ifdef cycloneiv
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specify
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if (ENA && ACLR !== 1'b0 && !SCLR && !SLOAD) (posedge CLK => (Q : DATAIN)) = 731;
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if (ENA && SCLR) (posedge CLK => (Q : 1'b0)) = 890;
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@ -82,7 +82,7 @@ module MISTRAL_ALUT6(input A, B, C, D, E, F, output Q);
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parameter [63:0] LUT = 64'h0000_0000_0000_0000;
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`ifdef cyclonev
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`ifdef cycloneiv
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specify
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(A => Q) = 605;
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(B => Q) = 583;
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@ -113,7 +113,7 @@ module MISTRAL_ALUT5(input A, B, C, D, E, output Q);
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parameter [31:0] LUT = 32'h0000_0000;
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`ifdef cyclonev
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`ifdef cycloneiv
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specify
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(A => Q) = 583;
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(B => Q) = 510;
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@ -142,7 +142,7 @@ module MISTRAL_ALUT4(input A, B, C, D, output Q);
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parameter [15:0] LUT = 16'h0000;
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`ifdef cyclonev
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`ifdef cycloneiv
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specify
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(A => Q) = 510;
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(B => Q) = 512;
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@ -169,7 +169,7 @@ module MISTRAL_ALUT3(input A, B, C, output Q);
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parameter [7:0] LUT = 8'h00;
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`ifdef cyclonev
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`ifdef cycloneiv
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specify
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(A => Q) = 510;
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(B => Q) = 400;
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@ -194,7 +194,7 @@ module MISTRAL_ALUT2(input A, B, output Q);
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parameter [3:0] LUT = 4'h0;
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`ifdef cyclonev
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`ifdef cycloneiv
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specify
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(A => Q) = 400;
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(B => Q) = 97;
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@ -215,7 +215,7 @@ endmodule
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(* abc9_lut=1, lib_whitebox *)
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module MISTRAL_NOT(input A, output Q);
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`ifdef cyclonev
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`ifdef cycloneiv
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specify
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(A => Q) = 97;
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endspecify
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@ -236,7 +236,7 @@ module MISTRAL_ALUT_ARITH(input A, B, C, D0, D1, (* abc9_carry *) input CI, outp
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parameter LUT0 = 16'h0000;
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parameter LUT1 = 16'h0000;
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`ifdef cyclonev
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`ifdef cycloneiv
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specify
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(A => SO) = 1342;
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(B => SO) = 1323;
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@ -1,18 +0,0 @@
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bram MISTRAL_MLAB
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init 0 # TODO: Re-enable when Yosys remembers the original filename.
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abits 5
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dbits 1
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groups 2
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ports 1 1
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wrmode 1 0
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# write enable
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enable 1 0
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transp 0 0
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clocks 1 0
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clkpol 1 1
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endbram
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match MISTRAL_MLAB
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min efficiency 5
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make_outreg
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endmatch
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@ -539,7 +539,7 @@ output eccstatus;
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endmodule
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(* blackbox *)
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module cyclonev_mlab_cell(portaaddr, portadatain, portbaddr, portbdataout, ena0, clk0, clk1);
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module cycloneiv_mlab_cell(portaaddr, portadatain, portbaddr, portbdataout, ena0, clk0, clk1);
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parameter logical_ram_name = "";
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parameter logical_ram_depth = 32;
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@ -562,7 +562,7 @@ input ena0, clk0, clk1;
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endmodule
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(* blackbox *)
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module cyclonev_mac(ax, ay, resulta);
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module cycloneiv_mac(ax, ay, resulta);
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parameter ax_width = 9;
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parameter signed_max = "true";
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@ -594,7 +594,7 @@ output [result_a_width-1:0] resulta;
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endmodule
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(* blackbox *)
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module cyclonev_ram_block(portaaddr, portadatain, portawe, portbaddr, portbdataout, portbre, clk0);
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module cycloneiv_ram_block(portaaddr, portadatain, portawe, portbaddr, portbdataout, portbre, clk0);
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parameter operation_mode = "dual_port";
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parameter logical_ram_name = "";
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@ -1,7 +1,7 @@
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`ifdef cyclonev
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`define LCELL cyclonev_lcell_comb
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`define MAC cyclonev_mac
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`define MLAB cyclonev_mlab_cell
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`ifdef cycloneiv
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`define LCELL cycloneiv_lcell_comb
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`define MAC cycloneiv_mac
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`define MLAB cycloneiv_mlab_cell
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`endif
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`ifdef cyclone10gx
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`define LCELL cyclone10gx_lcell_comb
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@ -140,7 +140,7 @@ output [CFG_DBITS-1:0] B1DATA;
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// Much like the MLAB, the M10K has mem_init[01234] parameters which would let
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// you initialise the RAM cell via hex literals. If they were implemented.
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cyclonev_ram_block #(
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cycloneiv_ram_block #(
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.operation_mode("dual_port"),
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.logical_ram_name(_TECHMAP_CELLNAME_),
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.port_a_address_width(CFG_ABITS),
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