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Update RTLIL text representation docs
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@ -63,6 +63,10 @@ significant bit first. Bits may be any of:
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- ``m``: A marked bit (internal use only)
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- ``-``: A don't care value
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When the bit representation has fewer bits than the width, it is padded to the width with
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the most significant explicit bit, or ``0`` if the most significant explicit bit is ``1``,
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or ``x`` if there are no explicit bits.
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An *integer* is simply a signed integer value in decimal format. **Warning:**
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Integer constants are limited to 32 bits. That is, they may only be in the range
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:math:`[-2147483648, 2147483648)`. Integers outside this range will result in an
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@ -133,6 +137,7 @@ wires, memories, cells, processes, and connections.
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<module> ::= <attr-stmt>* <module-stmt> <module-body> <module-end-stmt>
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<module-stmt> ::= module <id> <eol>
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<module-body> ::= (<param-stmt>
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| <conn-stmt>
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| <wire>
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| <memory>
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| <cell>
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@ -170,6 +175,11 @@ See :ref:`sec:rtlil_sigspec` for an overview of signal specifications.
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| <sigspec> [ <integer> (:<integer>)? ]
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| { <sigspec>* }
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When a ``<wire-id>`` is specified, the wire must have been previously declared.
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When a signal slice is specified, the left-hand integer must be greather than or
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equal to the right-hand integer.
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Connections
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^^^^^^^^^^^
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@ -268,7 +278,7 @@ may have zero or more attributes.
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.. code:: BNF
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<switch> ::= <switch-stmt> <case>* <switch-end-stmt>
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<switch-stmt> := <attr-stmt>* switch <sigspec> <eol>
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<switch-stmt> ::= <attr-stmt>* switch <sigspec> <eol>
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<case> ::= <attr-stmt>* <case-stmt> <case-body>
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<case-stmt> ::= case <compare>? <eol>
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<compare> ::= <sigspec> (, <sigspec>)*
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@ -295,3 +305,4 @@ be:
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| sync always <eol>
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<sync-type> ::= low | high | posedge | negedge | edge
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<update-stmt> ::= update <dest-sigspec> <src-sigspec> <eol>
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| <attr-stmt>* memwr <id> <sigspec> <sigspec> <sigspec> <constant> <eol>
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