From f45255f5a234c46d84b2ac240dbeb86b10f299be Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 5 Aug 2025 12:23:11 +1200 Subject: [PATCH 1/5] tests: More autoname tests --- tests/various/autoname.ys | 176 +++++++++++++++++++++++++++++++++++++- 1 file changed, 172 insertions(+), 4 deletions(-) diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys index f12fb7995..88d0837d9 100644 --- a/tests/various/autoname.ys +++ b/tests/various/autoname.ys @@ -1,10 +1,11 @@ +# prefer output name +design -reset read_rtlil < Date: Tue, 5 Aug 2025 12:24:05 +1200 Subject: [PATCH 2/5] autoname.cc: Avoid int overflow --- passes/cmds/autoname.cc | 67 ++++++++++++++++++++++++++--------------- 1 file changed, 42 insertions(+), 25 deletions(-) diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc index 737bd3e58..75e54f4b1 100644 --- a/passes/cmds/autoname.cc +++ b/passes/cmds/autoname.cc @@ -22,11 +22,24 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -int autoname_worker(Module *module, const dict& wire_score) +typedef struct name_proposal { + string name; + unsigned int score; + name_proposal() : name(""), score(-1) { } + name_proposal(string name, unsigned int score) : name(name), score(score) { } + bool operator<(const name_proposal &other) const { + if (score != other.score) + return score < other.score; + else + return name.length() < other.name.length(); + } +} name_proposal; + +int autoname_worker(Module *module, const dict& wire_score) { - dict> proposed_cell_names; - dict> proposed_wire_names; - int best_score = -1; + dict proposed_cell_names; + dict proposed_wire_names; + name_proposal best_name; for (auto cell : module->selected_cells()) { if (cell->name[0] == '$') { @@ -36,14 +49,14 @@ int autoname_worker(Module *module, const dict& wire_score) if (bit.wire != nullptr && bit.wire->name[0] != '$') { if (suffix.empty()) suffix = stringf("_%s_%s", log_id(cell->type), log_id(conn.first)); - string new_name(bit.wire->name.str() + suffix); - int score = wire_score.at(bit.wire); - if (cell->output(conn.first)) score = 0; - score = 10000*score + new_name.size(); - if (!proposed_cell_names.count(cell) || score < proposed_cell_names.at(cell).first) { - if (best_score < 0 || score < best_score) - best_score = score; - proposed_cell_names[cell] = make_pair(score, new_name); + name_proposal proposed_name( + bit.wire->name.str() + suffix, + cell->output(conn.first) ? 0 : wire_score.at(bit.wire) + ); + if (!proposed_cell_names.count(cell) || proposed_name < proposed_cell_names.at(cell)) { + if (proposed_name < best_name) + best_name = proposed_name; + proposed_cell_names[cell] = proposed_name; } } } @@ -54,32 +67,36 @@ int autoname_worker(Module *module, const dict& wire_score) if (bit.wire != nullptr && bit.wire->name[0] == '$' && !bit.wire->port_id) { if (suffix.empty()) suffix = stringf("_%s", log_id(conn.first)); - string new_name(cell->name.str() + suffix); - int score = wire_score.at(bit.wire); - if (cell->output(conn.first)) score = 0; - score = 10000*score + new_name.size(); - if (!proposed_wire_names.count(bit.wire) || score < proposed_wire_names.at(bit.wire).first) { - if (best_score < 0 || score < best_score) - best_score = score; - proposed_wire_names[bit.wire] = make_pair(score, new_name); + name_proposal proposed_name( + cell->name.str() + suffix, + cell->output(conn.first) ? 0 : wire_score.at(bit.wire) + ); + if (!proposed_wire_names.count(bit.wire) || proposed_name < proposed_wire_names.at(bit.wire)) { + if (proposed_name < best_name) + best_name = proposed_name; + proposed_wire_names[bit.wire] = proposed_name; } } } } } + // compare against double best score for following comparisons so we don't + // pre-empt a future iteration + best_name.score *= 2; + for (auto &it : proposed_cell_names) { - if (best_score*2 < it.second.first) + if (best_name < it.second) continue; - IdString n = module->uniquify(IdString(it.second.second)); + IdString n = module->uniquify(IdString(it.second.name)); log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); module->rename(it.first, n); } for (auto &it : proposed_wire_names) { - if (best_score*2 < it.second.first) + if (best_name < it.second) continue; - IdString n = module->uniquify(IdString(it.second.second)); + IdString n = module->uniquify(IdString(it.second.name)); log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); module->rename(it.first, n); } @@ -115,7 +132,7 @@ struct AutonamePass : public Pass { for (auto module : design->selected_modules()) { - dict wire_score; + dict wire_score; for (auto cell : module->selected_cells()) for (auto &conn : cell->connections()) for (auto bit : conn.second) From bc77b6213b1db0455ef443a5a044b5160a219145 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Sat, 9 Aug 2025 10:52:52 +1200 Subject: [PATCH 3/5] autoname: Fix selection arg --- passes/cmds/autoname.cc | 1 + tests/various/autoname.ys | 9 ++++++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc index 75e54f4b1..d2ff568c3 100644 --- a/passes/cmds/autoname.cc +++ b/passes/cmds/autoname.cc @@ -127,6 +127,7 @@ struct AutonamePass : public Pass { // } break; } + extra_args(args, argidx, design); log_header(design, "Executing AUTONAME pass.\n"); diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys index 88d0837d9..29ca81bbe 100644 --- a/tests/various/autoname.ys +++ b/tests/various/autoname.ys @@ -171,11 +171,14 @@ module \top end end EOT -# wires all named for being cell outputs +# wires are named for being cell outputs logger -expect log "Rename wire .d in top to or_Y" 1 +logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1 +debug autoname t:$or +logger -check-expected + # $name gets shortest name (otherwise bcd_$__unknown_B) logger -expect log "Rename cell .name in top to a_.__unknown_A" 1 -logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1 # another output wire logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1 # $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A) @@ -183,5 +186,5 @@ logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1 # $c gets shortest name, since the cell driving it doesn't have known port # directions logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1 -debug autoname t:$and +debug autoname logger -check-expected From fef6bdae6cda277a022381c2f325ba374a94f377 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 26 Sep 2025 11:05:50 +1200 Subject: [PATCH 4/5] autoname.cc: Return number of renames Was previously the number of proposed renames, but since renames can be skipped this causes the final count to differ from the number of actually renamed objects. Check counts in `tests/various/autoname.ys`. --- passes/cmds/autoname.cc | 5 ++++- tests/various/autoname.ys | 6 ++++++ 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc index d2ff568c3..1ad2eab3c 100644 --- a/passes/cmds/autoname.cc +++ b/passes/cmds/autoname.cc @@ -81,6 +81,7 @@ int autoname_worker(Module *module, const dict& wire_score) } } + int count = 0; // compare against double best score for following comparisons so we don't // pre-empt a future iteration best_name.score *= 2; @@ -91,6 +92,7 @@ int autoname_worker(Module *module, const dict& wire_score) IdString n = module->uniquify(IdString(it.second.name)); log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); module->rename(it.first, n); + count++; } for (auto &it : proposed_wire_names) { @@ -99,9 +101,10 @@ int autoname_worker(Module *module, const dict& wire_score) IdString n = module->uniquify(IdString(it.second.name)); log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); module->rename(it.first, n); + count++; } - return proposed_cell_names.size() + proposed_wire_names.size(); + return count; } struct AutonamePass : public Pass { diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys index 29ca81bbe..fccecb1c2 100644 --- a/tests/various/autoname.ys +++ b/tests/various/autoname.ys @@ -18,6 +18,7 @@ module \top end EOT logger -expect log "Rename cell .name in top to y_.and_Y" 1 +logger -expect log "Renamed 1 objects" 1 debug autoname logger -check-expected @@ -42,6 +43,7 @@ module \top end EOT logger -expect log "Rename cell .name in top to ab_.or_A" 1 +logger -expect log "Renamed 1 objects" 1 debug autoname logger -check-expected @@ -78,6 +80,7 @@ end EOT logger -expect log "Rename cell .name in top to bcd_.and_B" 1 logger -expect log "Rename cell .name2 in top to c_has_a_long_name_.or_B" 1 +logger -expect log "Renamed 2 objects" 1 debug autoname logger -check-expected @@ -113,6 +116,7 @@ end EOT logger -expect log "Rename cell .name in top to y_.and_Y" 1 logger -expect log "Rename cell .name2 in top to y_.and_Y_1" 1 +logger -expect log "Renamed 2 objects" 1 debug autoname logger -check-expected @@ -174,6 +178,7 @@ EOT # wires are named for being cell outputs logger -expect log "Rename wire .d in top to or_Y" 1 logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1 +logger -expect log "Renamed 2 objects" 1 debug autoname t:$or logger -check-expected @@ -186,5 +191,6 @@ logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1 # $c gets shortest name, since the cell driving it doesn't have known port # directions logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1 +logger -expect log "Renamed 4 objects" 1 debug autoname logger -check-expected From 941ba3b7454a2f2ccaf8fdf70489e5c3f4136195 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 26 Sep 2025 11:27:17 +1200 Subject: [PATCH 5/5] autoname.ys: Extra check for rename order Disabling comparison with best score will cause this check to fail. Preferred names will not be possible if $name2 has not yet been renamed. --- tests/various/autoname.ys | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/tests/various/autoname.ys b/tests/various/autoname.ys index fccecb1c2..7df1571b2 100644 --- a/tests/various/autoname.ys +++ b/tests/various/autoname.ys @@ -175,6 +175,8 @@ module \top end end EOT +design -save order_test + # wires are named for being cell outputs logger -expect log "Rename wire .d in top to or_Y" 1 logger -expect log "Rename cell .name2 in top to or_Y_.or_B" 1 @@ -186,11 +188,18 @@ logger -check-expected logger -expect log "Rename cell .name in top to a_.__unknown_A" 1 # another output wire logger -expect log "Rename wire .e in top to or_Y_.or_B_Y" 1 -# $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A) -logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1 -# $c gets shortest name, since the cell driving it doesn't have known port -# directions -logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1 logger -expect log "Renamed 4 objects" 1 debug autoname logger -check-expected + +# don't rename prematurely (some objects should be named after $name2) +design -load order_test + +# $c gets shortest name, since the cell driving it doesn't have known port +# directions (otherwise a_$__unknown_A_Y) +logger -expect log "Rename wire .c in top to or_Y_.or_B_A" 1 +# $name3 named for lowest fanout wire (otherwise a_$__unknown_A_Y_$and_A) +logger -expect log "Rename cell .name3 in top to or_Y_.or_B_Y_.and_B" 1 +logger -expect log "Renamed 6 objects" 1 +debug autoname +logger -check-expected