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	Fixed shift ops with large right hand side
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					 3 changed files with 50 additions and 10 deletions
				
			
		|  | @ -241,7 +241,7 @@ struct SatGen | |||
| 			{ | ||||
| 				std::vector<int> tmp_shifted(tmp.size()); | ||||
| 				for (size_t j = 0; j < tmp.size(); j++) { | ||||
| 					int idx = j + (1 << i) * (shift_left ? -1 : +1); | ||||
| 					int idx = j + (1 << (i > 30 ? 30 : i)) * (shift_left ? -1 : +1); | ||||
| 					tmp_shifted.at(j) = (0 <= idx && idx < int(tmp.size())) ? tmp.at(idx) : sign_extend ? tmp.back() : ez->FALSE; | ||||
| 				} | ||||
| 				tmp = ez->vec_ite(b.at(i), tmp_shifted, tmp); | ||||
|  |  | |||
|  | @ -446,7 +446,7 @@ generate | |||
| 		assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result; | ||||
| 		\$shift #( | ||||
| 			.WIDTH(WIDTH), | ||||
| 			.SHIFT(0 - (2 ** i)) | ||||
| 			.SHIFT(0 - (2 ** (i > 30 ? 30 : i))) | ||||
| 		) sh ( | ||||
| 			.X(0), | ||||
| 			.A(unshifted), | ||||
|  | @ -499,7 +499,7 @@ generate | |||
| 		assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result; | ||||
| 		\$shift #( | ||||
| 			.WIDTH(WIDTH), | ||||
| 			.SHIFT(2 ** i) | ||||
| 			.SHIFT(2 ** (i > 30 ? 30 : i)) | ||||
| 		) sh ( | ||||
| 			.X(0), | ||||
| 			.A(unshifted), | ||||
|  | @ -552,7 +552,7 @@ generate | |||
| 		assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result; | ||||
| 		\$shift #( | ||||
| 			.WIDTH(WIDTH), | ||||
| 			.SHIFT(0 - (2 ** i)) | ||||
| 			.SHIFT(0 - (2 ** (i > 30 ? 30 : i))) | ||||
| 		) sh ( | ||||
| 			.X(0), | ||||
| 			.A(unshifted), | ||||
|  | @ -614,7 +614,7 @@ generate | |||
| 		assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result; | ||||
| 		\$shift #( | ||||
| 			.WIDTH(WIDTH), | ||||
| 			.SHIFT(2 ** i) | ||||
| 			.SHIFT(2 ** (i > 30 ? 30 : i)) | ||||
| 		) sh ( | ||||
| 			.X(A_SIGNED && A[A_WIDTH-1]), | ||||
| 			.A(unshifted), | ||||
|  | @ -800,7 +800,7 @@ input [B_WIDTH-1:0] B; | |||
| output Y; | ||||
| 
 | ||||
| wire carry, carry_sign; | ||||
| wire [WIDTH-1:0] A_buf, B_buf, Y_buf; | ||||
| wire [WIDTH-1:0] A_buf, B_buf; | ||||
| \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf)); | ||||
| \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf)); | ||||
| 
 | ||||
|  | @ -825,7 +825,7 @@ input [B_WIDTH-1:0] B; | |||
| output Y; | ||||
| 
 | ||||
| wire carry, carry_sign; | ||||
| wire [WIDTH-1:0] A_buf, B_buf, Y_buf; | ||||
| wire [WIDTH-1:0] A_buf, B_buf; | ||||
| \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf)); | ||||
| \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf)); | ||||
| 
 | ||||
|  |  | |||
|  | @ -3,8 +3,48 @@ | |||
| // https://github.com/cliffordwolf/VlogHammer | ||||
| 
 | ||||
| module test01(a, y); | ||||
| 	input [7:0] a; | ||||
| 	output [3:0] y; | ||||
| 	assign y = ~a >> 4; | ||||
|   input [7:0] a; | ||||
|   output [3:0] y; | ||||
|   assign y = ~a >> 4; | ||||
| endmodule | ||||
| 
 | ||||
| module test02(a, y); | ||||
|   input signed [3:0] a; | ||||
|   output signed [4:0] y; | ||||
|   assign y = (~a) >> 1; | ||||
| endmodule | ||||
| 
 | ||||
| module test03(a, b, y); | ||||
|   input [2:0] a; | ||||
|   input signed [1:0] b; | ||||
|   output y; | ||||
|   assign y = ~(a >>> 1) == b; | ||||
| endmodule | ||||
| 
 | ||||
| module test04(a, y); | ||||
|   input a; | ||||
|   output [1:0] y; | ||||
|   assign y = ~(a - 1'b0); | ||||
| endmodule | ||||
| 
 | ||||
| module test05(a, y); | ||||
|   input a; | ||||
|   output y; | ||||
|   assign y = 12345 >> {a, 32'd0}; | ||||
| endmodule | ||||
| 
 | ||||
| module test06(a, b, c, y); | ||||
|   input signed [3:0] a; | ||||
|   input signed [1:0] b; | ||||
|   input signed [1:0] c; | ||||
|   output [5:0] y; | ||||
|   assign y = (a >> b) >>> c; | ||||
| endmodule | ||||
| 
 | ||||
| module test07(a, b, y); | ||||
|   input signed [1:0] a; | ||||
|   input signed [2:0] b; | ||||
|   output y; | ||||
|   assign y = 2'b11 != a+b; | ||||
| endmodule | ||||
| 
 | ||||
|  |  | |||
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