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51 lines
852 B
Verilog
51 lines
852 B
Verilog
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// test cases found using vloghammer
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// https://github.com/cliffordwolf/VlogHammer
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module test01(a, y);
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input [7:0] a;
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output [3:0] y;
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assign y = ~a >> 4;
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endmodule
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module test02(a, y);
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input signed [3:0] a;
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output signed [4:0] y;
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assign y = (~a) >> 1;
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endmodule
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module test03(a, b, y);
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input [2:0] a;
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input signed [1:0] b;
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output y;
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assign y = ~(a >>> 1) == b;
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endmodule
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module test04(a, y);
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input a;
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output [1:0] y;
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assign y = ~(a - 1'b0);
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endmodule
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module test05(a, y);
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input a;
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output y;
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assign y = 12345 >> {a, 32'd0};
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endmodule
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module test06(a, b, c, y);
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input signed [3:0] a;
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input signed [1:0] b;
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input signed [1:0] c;
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output [5:0] y;
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assign y = (a >> b) >>> c;
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endmodule
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module test07(a, b, y);
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input signed [1:0] a;
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input signed [2:0] b;
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output y;
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assign y = 2'b11 != a+b;
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endmodule
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