mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-31 11:42:30 +00:00
Code Activity

Fixed shift ops with large right hand side

Browse source
This commit is contained in:
Clifford Wolf 2013-07-09 18:59:59 +02:00
parent e8da3ea7b6
commit 7daeee340a
3 changed files with 50 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

2
kernel/satgen.h
View file

@ -241,7 +241,7 @@ struct SatGen
{ {
std::vector<int> tmp_shifted(tmp.size()); std::vector<int> tmp_shifted(tmp.size());
for (size_t j = 0; j < tmp.size(); j++) { for (size_t j = 0; j < tmp.size(); j++) {
int idx = j + (1 << i) * (shift_left ? -1 : +1); int idx = j + (1 << (i > 30 ? 30 : i)) * (shift_left ? -1 : +1);
tmp_shifted.at(j) = (0 <= idx && idx < int(tmp.size())) ? tmp.at(idx) : sign_extend ? tmp.back() : ez->FALSE; tmp_shifted.at(j) = (0 <= idx && idx < int(tmp.size())) ? tmp.at(idx) : sign_extend ? tmp.back() : ez->FALSE;
} }
tmp = ez->vec_ite(b.at(i), tmp_shifted, tmp); tmp = ez->vec_ite(b.at(i), tmp_shifted, tmp);

12
techlibs/stdcells.v
View file

@ -446,7 +446,7 @@ generate
assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result; assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
\$shift #( \$shift #(
.WIDTH(WIDTH), .WIDTH(WIDTH),
.SHIFT(0 - (2 ** i)) .SHIFT(0 - (2 ** (i > 30 ? 30 : i)))
) sh ( ) sh (
.X(0), .X(0),
.A(unshifted), .A(unshifted),
@ -499,7 +499,7 @@ generate
assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result; assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
\$shift #( \$shift #(
.WIDTH(WIDTH), .WIDTH(WIDTH),
.SHIFT(2 ** i) .SHIFT(2 ** (i > 30 ? 30 : i))
) sh ( ) sh (
.X(0), .X(0),
.A(unshifted), .A(unshifted),
@ -552,7 +552,7 @@ generate
assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result; assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
\$shift #( \$shift #(
.WIDTH(WIDTH), .WIDTH(WIDTH),
.SHIFT(0 - (2 ** i)) .SHIFT(0 - (2 ** (i > 30 ? 30 : i)))
) sh ( ) sh (
.X(0), .X(0),
.A(unshifted), .A(unshifted),
@ -614,7 +614,7 @@ generate
assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result; assign chain[WIDTH*(i+1) + WIDTH-1 : WIDTH*(i+1)] = result;
\$shift #( \$shift #(
.WIDTH(WIDTH), .WIDTH(WIDTH),
.SHIFT(2 ** i) .SHIFT(2 ** (i > 30 ? 30 : i))
) sh ( ) sh (
.X(A_SIGNED && A[A_WIDTH-1]), .X(A_SIGNED && A[A_WIDTH-1]),
.A(unshifted), .A(unshifted),
@ -800,7 +800,7 @@ input [B_WIDTH-1:0] B;
output Y; output Y;
wire carry, carry_sign; wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf, Y_buf; wire [WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf)); \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));
@ -825,7 +825,7 @@ input [B_WIDTH-1:0] B;
output Y; output Y;
wire carry, carry_sign; wire carry, carry_sign;
wire [WIDTH-1:0] A_buf, B_buf, Y_buf; wire [WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf)); \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf)); \$pos #(.A_SIGNED(A_SIGNED && B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(WIDTH)) B_conv (.A(B), .Y(B_buf));

46
tests/simple/vloghammer.v
View file

@ -3,8 +3,48 @@
// https://github.com/cliffordwolf/VlogHammer // https://github.com/cliffordwolf/VlogHammer
module test01(a, y); module test01(a, y);
input [7:0] a; input [7:0] a;
output [3:0] y; output [3:0] y;
assign y = ~a >> 4; assign y = ~a >> 4;
endmodule
module test02(a, y);
input signed [3:0] a;
output signed [4:0] y;
assign y = (~a) >> 1;
endmodule
module test03(a, b, y);
input [2:0] a;
input signed [1:0] b;
output y;
assign y = ~(a >>> 1) == b;
endmodule
module test04(a, y);
input a;
output [1:0] y;
assign y = ~(a - 1'b0);
endmodule
module test05(a, y);
input a;
output y;
assign y = 12345 >> {a, 32'd0};
endmodule
module test06(a, b, c, y);
input signed [3:0] a;
input signed [1:0] b;
input signed [1:0] c;
output [5:0] y;
assign y = (a >> b) >>> c;
endmodule
module test07(a, b, y);
input signed [1:0] a;
input signed [2:0] b;
output y;
assign y = 2'b11 != a+b;
endmodule endmodule