From 7cfdf4ffa7698fa40aae401c2b8b159a6e37011a Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 12 Feb 2020 12:16:01 -0800
Subject: [PATCH] verilog: fix $specify3 check
---
frontends/ast/genrtlil.cc | 18 +++++++++++-------
tests/various/specify.v | 7 +++++++
2 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 94f5c0a04..05a5b45b8 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1559,21 +1559,25 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
log_file_error(filename, linenum, "Attribute `%s' with non-constant value.\n", attr.first.c_str());
cell->attributes[attr.first] = attr.second->asAttrConst();
}
- if (cell->type.in("$specify2", "$specify3")) {
+ if (cell->type == "$specify2") {
int src_width = GetSize(cell->getPort("\\SRC"));
int dst_width = GetSize(cell->getPort("\\DST"));
bool full = cell->getParam("\\FULL").as_bool();
if (!full && src_width != dst_width)
log_file_error(filename, linenum, "Parallel specify SRC width does not match DST width.\n");
- if (cell->type == "$specify3") {
- int dat_width = GetSize(cell->getPort("\\DAT"));
- if (dat_width != dst_width)
- log_file_error(filename, linenum, "Specify DAT width does not match DST width.\n");
- }
cell->setParam("\\SRC_WIDTH", Const(src_width));
cell->setParam("\\DST_WIDTH", Const(dst_width));
}
- if (cell->type == "$specrule") {
+ else if (cell->type == "$specify3") {
+ int dat_width = GetSize(cell->getPort("\\DAT"));
+ int dst_width = GetSize(cell->getPort("\\DST"));
+ if (dat_width != dst_width)
+ log_file_error(filename, linenum, "Specify DAT width does not match DST width.\n");
+ int src_width = GetSize(cell->getPort("\\SRC"));
+ cell->setParam("\\SRC_WIDTH", Const(src_width));
+ cell->setParam("\\DST_WIDTH", Const(dst_width));
+ }
+ else if (cell->type == "$specrule") {
int src_width = GetSize(cell->getPort("\\SRC"));
int dst_width = GetSize(cell->getPort("\\DST"));
cell->setParam("\\SRC_WIDTH", Const(src_width));
diff --git a/tests/various/specify.v b/tests/various/specify.v
index 5d44d78f7..e4dd132f1 100644
--- a/tests/various/specify.v
+++ b/tests/various/specify.v
@@ -37,3 +37,10 @@ specify
(posedge clk *> (q +: d)) = (3,1);
endspecify
endmodule
+
+module test3(input clk, input [1:0] d, output [1:0] q);
+specify
+ (posedge clk => (q +: d)) = (3,1);
+ (posedge clk *> (q +: d)) = (3,1);
+endspecify
+endmodule