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fixup! abstract: -state MVP
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@ -20,8 +20,7 @@ bool abstract_state(Module* mod, Cell* cell, Wire* enable, bool enable_pol) {
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auto anyseq = mod->Anyseq(NEW_ID, ff.width);
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if (ff.has_aload) {
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// aload := enable ? anyseq : aload
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// ff.pol_aload = enable_pol;
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// ad := enable ? anyseq : ad
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Wire* abstracted_ad = mod->addWire(NEW_ID, ff.sig_ad.size());
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SigSpec mux_a, mux_b;
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if (enable_pol) {
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@ -38,6 +37,7 @@ bool abstract_state(Module* mod, Cell* cell, Wire* enable, bool enable_pol) {
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abstracted_ad);
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ff.sig_ad = abstracted_ad;
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}
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// d := enable ? anyseq : d
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Wire* abstracted_d = mod->addWire(NEW_ID, ff.sig_d.size());
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SigSpec mux_a, mux_b;
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if (enable_pol) {
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