Update passes/fsm to avoid bits()

passes/fsm/fsm_extract.cc

@@ -171,7 +171,7 @@ undef_bit_in_next_state:
 			if (tr.ctrl_in.at(it.second) == State::S1 && exclusive_ctrls.count(it.first) != 0)
 				for (auto &dc_bit : exclusive_ctrls.at(it.first))
 					if (ctrl_in_bit_indices.count(dc_bit))
-						tr.ctrl_in.bits().at(ctrl_in_bit_indices.at(dc_bit)) = RTLIL::State::Sa;
+						tr.ctrl_in.set(ctrl_in_bit_indices.at(dc_bit), RTLIL::State::Sa);
 
 		RTLIL::Const log_state_in = RTLIL::Const(RTLIL::State::Sx, fsm_data.state_bits);
 		if (state_in >= 0)

passes/fsm/fsm_map.cc

@@ -176,7 +176,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
 		state_dff->type = ID($adff);
 		state_dff->parameters[ID::ARST_POLARITY] = fsm_cell->parameters[ID::ARST_POLARITY];
 		state_dff->parameters[ID::ARST_VALUE] = fsm_data.state_table[fsm_data.reset_state];
-		for (auto &bit : state_dff->parameters[ID::ARST_VALUE].bits())
+		for (auto bit : state_dff->parameters[ID::ARST_VALUE])
 			if (bit != RTLIL::State::S1)
 				bit = RTLIL::State::S0;
 		state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST));

passes/fsm/fsm_opt.cc

@@ -169,13 +169,16 @@ struct FsmOpt
 
 				for (auto tr : fsm_data.transition_table)
 				{
-					RTLIL::State &si = tr.ctrl_in.bits()[i];
+					RTLIL::State si = tr.ctrl_in[i];
-					RTLIL::State &sj = tr.ctrl_in.bits()[j];
+					RTLIL::State sj = tr.ctrl_in[j];
 
-					if (si > RTLIL::State::S1)
+					if (si > RTLIL::State::S1) {
 						si = sj;
-					else if (sj > RTLIL::State::S1)
+						tr.ctrl_in.set(i, si);
+					} else if (sj > RTLIL::State::S1) {
 						sj = si;
+						tr.ctrl_in.set(j, sj);
+					}
 
 					if (si == sj) {
 						RTLIL::SigSpec tmp(tr.ctrl_in);
@@ -207,8 +210,8 @@ struct FsmOpt
 
 				for (auto tr : fsm_data.transition_table)
 				{
-					RTLIL::State &si = tr.ctrl_in.bits()[i];
+					RTLIL::State si = tr.ctrl_in[i];
-					RTLIL::State &sj = tr.ctrl_out.bits()[j];
+					RTLIL::State sj = tr.ctrl_out[j];
 
 					if (si > RTLIL::State::S1 || si == sj) {
 						RTLIL::SigSpec tmp(tr.ctrl_in);
@@ -240,14 +243,14 @@ struct FsmOpt
 			RTLIL::Const other_pattern = pattern;
 
 			if (pattern[bit] == RTLIL::State::S1)
-				other_pattern.bits()[bit] = RTLIL::State::S0;
+				other_pattern.set(bit, RTLIL::State::S0);
 			else
-				other_pattern.bits()[bit] = RTLIL::State::S1;
+				other_pattern.set(bit, RTLIL::State::S1);
 
 			if (set.count(other_pattern) > 0) {
 				log("  Merging pattern %s and %s from group (%d %d %s).\n", log_signal(pattern), log_signal(other_pattern),
 						tr.state_in, tr.state_out, log_signal(tr.ctrl_out));
-				other_pattern.bits()[bit] = RTLIL::State::Sa;
+				other_pattern.set(bit, RTLIL::State::Sa);
 				new_set.insert(other_pattern);
 				did_something = true;
 				continue;

passes/fsm/fsm_recode.cc

@@ -106,7 +106,7 @@ static void fsm_recode(RTLIL::Cell *cell, RTLIL::Module *module, FILE *fm_set_fs
 
 		if (encoding == "one-hot") {
 			new_code = RTLIL::Const(RTLIL::State::Sa, fsm_data.state_bits);
-			new_code.bits()[state_idx] = RTLIL::State::S1;
+			new_code.set(state_idx, RTLIL::State::S1);
 		} else
 		if (encoding == "binary") {
 			new_code = RTLIL::Const(state_idx, fsm_data.state_bits);

passes/fsm/fsmdata.h

@@ -45,35 +45,27 @@ struct FsmData
 		cell->parameters[ID::STATE_NUM] = RTLIL::Const(state_table.size());
 		cell->parameters[ID::STATE_NUM_LOG2] = RTLIL::Const(state_num_log2);
 		cell->parameters[ID::STATE_RST] = RTLIL::Const(reset_state);
-		cell->parameters[ID::STATE_TABLE] = RTLIL::Const();
+		RTLIL::Const cell_state_table;
-
+		for (const RTLIL::Const &c : state_table)
-		for (int i = 0; i < int(state_table.size()); i++) {
+			cell_state_table.append(c);
-			std::vector<RTLIL::State> &bits_table = cell->parameters[ID::STATE_TABLE].bits();
+		cell->parameters[ID::STATE_TABLE] = std::move(cell_state_table);
-			std::vector<RTLIL::State> &bits_state = state_table[i].bits();
-			bits_table.insert(bits_table.end(), bits_state.begin(), bits_state.end());
-		}
 
 		cell->parameters[ID::TRANS_NUM] = RTLIL::Const(transition_table.size());
-		cell->parameters[ID::TRANS_TABLE] = RTLIL::Const();
+		RTLIL::Const cell_trans_table;
 		for (int i = 0; i < int(transition_table.size()); i++)
 		{
-			std::vector<RTLIL::State> &bits_table = cell->parameters[ID::TRANS_TABLE].bits();
 			transition_t &tr = transition_table[i];
 
 			RTLIL::Const const_state_in = RTLIL::Const(tr.state_in, state_num_log2);
 			RTLIL::Const const_state_out = RTLIL::Const(tr.state_out, state_num_log2);
-			std::vector<RTLIL::State> &bits_state_in = const_state_in.bits();
-			std::vector<RTLIL::State> &bits_state_out = const_state_out.bits();
-
-			std::vector<RTLIL::State> &bits_ctrl_in = tr.ctrl_in.bits();
-			std::vector<RTLIL::State> &bits_ctrl_out = tr.ctrl_out.bits();
 
 			// append lsb first
-			bits_table.insert(bits_table.end(), bits_ctrl_out.begin(), bits_ctrl_out.end());
+			cell_trans_table.append(tr.ctrl_out);
-			bits_table.insert(bits_table.end(), bits_state_out.begin(), bits_state_out.end());
+			cell_trans_table.append(const_state_out);
-			bits_table.insert(bits_table.end(), bits_ctrl_in.begin(), bits_ctrl_in.end());
+			cell_trans_table.append(tr.ctrl_in);
-			bits_table.insert(bits_table.end(), bits_state_in.begin(), bits_state_in.end());
+			cell_trans_table.append(const_state_in);
 		}
+		cell->parameters[ID::TRANS_TABLE] = std::move(cell_trans_table);
 	}
 
 	void copy_from_cell(RTLIL::Cell *cell)
@@ -95,25 +87,18 @@ struct FsmData
 		const RTLIL::Const &trans_table = cell->parameters[ID::TRANS_TABLE];
 
 		for (int i = 0; i < state_num; i++) {
-			RTLIL::Const state_code;
+			int off_begin = i*state_bits;
-			int off_begin = i*state_bits, off_end = off_begin + state_bits;
+			RTLIL::Const state_code = state_table.extract(off_begin, state_bits);
-			state_code.bits().insert(state_code.bits().begin(), state_table.begin()+off_begin, state_table.begin()+off_end);
 			this->state_table.push_back(state_code);
 		}
 
 		for (int i = 0; i < trans_num; i++)
 		{
-			auto off_ctrl_out = trans_table.begin() + i*(num_inputs+num_outputs+2*state_num_log2);
+			int base_offset = i*(num_inputs+num_outputs+2*state_num_log2);
-			auto off_state_out = off_ctrl_out + num_outputs;
+			RTLIL::Const ctrl_out = trans_table.extract(base_offset, num_outputs);
-			auto off_ctrl_in = off_state_out + state_num_log2;
+			RTLIL::Const state_out = trans_table.extract(base_offset + num_outputs, state_num_log2);
-			auto off_state_in = off_ctrl_in + num_inputs;
+			RTLIL::Const ctrl_in = trans_table.extract(base_offset + num_outputs + state_num_log2, num_inputs);
-			auto off_end = off_state_in + state_num_log2;
+			RTLIL::Const state_in = trans_table.extract(base_offset + num_outputs + state_num_log2 + num_inputs, state_num_log2);
-
-			RTLIL::Const state_in, state_out, ctrl_in, ctrl_out;
-			ctrl_out.bits().insert(ctrl_out.bits().begin(), off_ctrl_out, off_state_out);
-			state_out.bits().insert(state_out.bits().begin(), off_state_out, off_ctrl_in);
-			ctrl_in.bits().insert(ctrl_in.bits().begin(), off_ctrl_in, off_state_in);
-			state_in.bits().insert(state_in.bits().begin(), off_state_in, off_end);
 
 			transition_t tr;
 			tr.state_in = state_in.as_int();