mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-23 06:13:41 +00:00
Code Activity

Packed muxes have src attr for each constituent mux

Browse source
This commit is contained in:
Akash Levy 2025-03-05 06:09:40 -08:00
parent 8117ab228e
commit 7c1cb53c85
1 changed files with 2 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

3
passes/opt/muxpack.cc
View file

@ -288,6 +288,7 @@ struct MuxpackWorker
s_sig.append(module->LogicNot(NEW_ID2_SUFFIX("sel"), cursor_cell->getPort(ID::S), false, cell->get_src_attribute())); // SILIMATE: Improve the naming s_sig.append(module->LogicNot(NEW_ID2_SUFFIX("sel"), cursor_cell->getPort(ID::S), false, cell->get_src_attribute())); // SILIMATE: Improve the naming
} }
remove_cells.insert(cursor_cell); remove_cells.insert(cursor_cell);
first_cell->add_strpool_attribute(ID::src, cursor_cell->get_strpool_attribute(ID::src)); // SILIMATE: Improve src attribution
} }
if (make_excl) { if (make_excl) {
@ -328,7 +329,7 @@ struct MuxpackWorker
Wire *and_y = module->addWire(NEW_ID2_SUFFIX("and_y"), 1); Wire *and_y = module->addWire(NEW_ID2_SUFFIX("and_y"), 1);
module->addAnd(NEW_ID2_SUFFIX("sel"), sigbit, prevSigNot, and_y, false, last_cell->get_src_attribute()); module->addAnd(NEW_ID2_SUFFIX("sel"), sigbit, prevSigNot, and_y, false, last_cell->get_src_attribute());
decodedSelect.append(and_y); decodedSelect.append(and_y);
Wire *not_y = module->addWire(NEW_ID, 1); Wire *not_y = module->addWire(NEW_ID2_SUFFIX("not_y"), 1);
module->addNot(NEW_ID2_SUFFIX("not"), sigbit, not_y, false, last_cell->get_src_attribute()); module->addNot(NEW_ID2_SUFFIX("not"), sigbit, not_y, false, last_cell->get_src_attribute());
prevSigAnd = prevSigNot; prevSigAnd = prevSigNot;
prevSigNot = not_y; prevSigNot = not_y;