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tests: add cases covering full_case and parallel_case semantics

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This is @KrystalDelusion's suggestion in PR #5141 to verify
sensible implementation of all 4 possible full_case/parallel_case
combinations.

(Also including two similar tests to check the Verilog frontend
applies the correct attributes when given SystemVerilog
priority/unique case and if statements.)
This commit is contained in:
Gary Wong 2025-05-29 20:43:41 -06:00
parent 370d5871f4
commit 7b09dc31af
3 changed files with 165 additions and 0 deletions
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57
tests/proc/case_attr.ys Normal file
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read_verilog -sv << EOF
module top (input A, B, C, D, E, F, output reg W, X, Y, Z);
always @* begin
W = F;
(* full_case *)
case (C)
A: W = D;
B: W = E;
endcase
end
always @* begin
X = F;
case (C)
A: X = D;
B: X = E;
endcase
end
always @* begin
Y = F;
(* full_case, parallel_case *)
case (C)
A: Y = D;
B: Y = E;
endcase
end
always @* begin
Z = F;
(* parallel_case *)
case (C)
A: Z = D;
B: Z = E;
endcase
end
endmodule
EOF
prep
# For the ones which use full_case, the F signal shouldn't be included in
# the input cone of W and Y.
select -set full o:W o:Y %u %ci*
select -assert-none i:F @full %i
select -assert-count 1 o:X %ci* i:F %i
select -assert-count 1 o:Z %ci* i:F %i
# And for parallel_case there should be 1 $pmux compared to the 2 $mux
# cells without.
select -assert-none o:W %ci* t:$pmux %i
select -assert-none o:X %ci* t:$pmux %i
select -assert-count 1 o:Y %ci* t:$pmux %i
select -assert-count 1 o:Z %ci* t:$pmux %i
select -assert-count 2 o:W %ci* t:$mux %i
select -assert-count 2 o:X %ci* t:$mux %i
select -assert-none o:Y %ci* t:$mux %i
select -assert-none o:Z %ci* t:$mux %i

54
tests/verilog/unique_priority_case.ys Normal file
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read_verilog -sv << EOF
module top (input A, B, C, D, E, F, output reg W, X, Y, Z);
always_comb begin
W = F;
priority case (C)
A: W = D;
B: W = E;
endcase
end
always_comb begin
X = F;
case (C)
A: X = D;
B: X = E;
endcase
end
always_comb begin
Y = F;
unique case (C)
A: Y = D;
B: Y = E;
endcase
end
always_comb begin
Z = F;
unique0 case (C)
A: Z = D;
B: Z = E;
endcase
end
endmodule
EOF
prep
# For the ones which use priority/unique, the F signal shouldn't be included in
# the input cone of W and Y.
select -set full o:W o:Y %u %ci*
select -assert-none i:F @full %i
select -assert-count 1 o:X %ci* i:F %i
select -assert-count 1 o:Z %ci* i:F %i
# And for unique/unique0 there should be 1 $pmux compared to the 2 $mux
# cells without.
select -assert-none o:W %ci* t:$pmux %i
select -assert-none o:X %ci* t:$pmux %i
select -assert-count 1 o:Y %ci* t:$pmux %i
select -assert-count 1 o:Z %ci* t:$pmux %i
select -assert-count 2 o:W %ci* t:$mux %i
select -assert-count 2 o:X %ci* t:$mux %i
select -assert-none o:Y %ci* t:$mux %i
select -assert-none o:Z %ci* t:$mux %i

54
tests/verilog/unique_priority_if.ys Normal file
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read_verilog -sv << EOF
module top (input A, B, C, D, E, F, output reg W, X, Y, Z);
always_comb begin
W = F;
priority if (C == A)
W = D;
else if (C == B)
W = E;
end
always_comb begin
X = F;
if (C == A)
X = D;
else if (C == B)
X = E;
end
always_comb begin
Y = F;
unique if (C == A)
Y = D;
else if (C == B)
Y = E;
end
always_comb begin
Z = F;
unique0 if (C == A)
Z = D;
else if (C == B)
Z = E;
end
endmodule
EOF
prep
# For the ones which use priority/unique, the F signal shouldn't be included in
# the input cone of W and Y.
select -set full o:W o:Y %u %ci*
select -assert-none i:F @full %i
select -assert-count 1 o:X %ci* i:F %i
select -assert-count 1 o:Z %ci* i:F %i
# And for unique/unique0 there should be 1 $pmux compared to the 2 $mux
# cells without.
select -assert-none o:W %ci* t:$pmux %i
select -assert-none o:X %ci* t:$pmux %i
select -assert-count 1 o:Y %ci* t:$pmux %i
select -assert-count 1 o:Z %ci* t:$pmux %i
select -assert-count 2 o:W %ci* t:$mux %i
select -assert-count 2 o:X %ci* t:$mux %i
select -assert-none o:Y %ci* t:$mux %i
select -assert-none o:Z %ci* t:$mux %i