From 7b09dc31af5ca7319ec41b2c1e91dde44a5dce42 Mon Sep 17 00:00:00 2001
From: Gary Wong <gtw@gnu.org>
Date: Thu, 29 May 2025 20:43:41 -0600
Subject: [PATCH] tests: add cases covering full_case and parallel_case
 semantics

This is @KrystalDelusion's suggestion in PR #5141 to verify
sensible implementation of all 4 possible full_case/parallel_case
combinations.

(Also including two similar tests to check the Verilog frontend
applies the correct attributes when given SystemVerilog
priority/unique case and if statements.)
---
 tests/proc/case_attr.ys               | 57 +++++++++++++++++++++++++++
 tests/verilog/unique_priority_case.ys | 54 +++++++++++++++++++++++++
 tests/verilog/unique_priority_if.ys   | 54 +++++++++++++++++++++++++
 3 files changed, 165 insertions(+)
 create mode 100644 tests/proc/case_attr.ys
 create mode 100644 tests/verilog/unique_priority_case.ys
 create mode 100644 tests/verilog/unique_priority_if.ys

diff --git a/tests/proc/case_attr.ys b/tests/proc/case_attr.ys
new file mode 100644
index 000000000..63be79fe5
--- /dev/null
+++ b/tests/proc/case_attr.ys
@@ -0,0 +1,57 @@
+read_verilog -sv << EOF
+module top (input A, B, C, D, E, F, output reg W, X, Y, Z);
+	always @* begin
+		W = F;
+		(* full_case *)
+		case (C)
+			A: W = D;
+			B: W = E;
+		endcase
+	end
+
+	always @* begin
+		X = F;
+		case (C)
+			A: X = D;
+			B: X = E;
+		endcase
+	end
+
+	always @* begin
+		Y = F;
+		(* full_case, parallel_case *)
+		case (C)
+			A: Y = D;
+			B: Y = E;
+		endcase
+	end
+
+	always @* begin
+		Z = F;
+		(* parallel_case *)
+		case (C)
+			A: Z = D;
+			B: Z = E;
+		endcase
+	end
+endmodule
+EOF
+prep
+# For the ones which use full_case, the F signal shouldn't be included in
+# the input cone of W and Y.
+select -set full o:W o:Y %u %ci*
+select -assert-none i:F @full %i
+select -assert-count 1 o:X %ci* i:F %i
+select -assert-count 1 o:Z %ci* i:F %i
+
+# And for parallel_case there should be 1 $pmux compared to the 2 $mux
+# cells without.
+select -assert-none o:W %ci* t:$pmux %i
+select -assert-none o:X %ci* t:$pmux %i
+select -assert-count 1 o:Y %ci* t:$pmux %i
+select -assert-count 1 o:Z %ci* t:$pmux %i
+
+select -assert-count 2 o:W %ci* t:$mux %i
+select -assert-count 2 o:X %ci* t:$mux %i
+select -assert-none o:Y %ci* t:$mux %i
+select -assert-none o:Z %ci* t:$mux %i
diff --git a/tests/verilog/unique_priority_case.ys b/tests/verilog/unique_priority_case.ys
new file mode 100644
index 000000000..1f87fb19c
--- /dev/null
+++ b/tests/verilog/unique_priority_case.ys
@@ -0,0 +1,54 @@
+read_verilog -sv << EOF
+module top (input A, B, C, D, E, F, output reg W, X, Y, Z);
+	always_comb begin
+		W = F;
+		priority case (C)
+			A: W = D;
+			B: W = E;
+		endcase
+	end
+
+	always_comb begin
+		X = F;
+		case (C)
+			A: X = D;
+			B: X = E;
+		endcase
+	end
+
+	always_comb begin
+		Y = F;
+		unique case (C)
+			A: Y = D;
+			B: Y = E;
+		endcase
+	end
+
+	always_comb begin
+		Z = F;
+		unique0 case (C)
+			A: Z = D;
+			B: Z = E;
+		endcase
+	end
+endmodule
+EOF
+prep
+# For the ones which use priority/unique, the F signal shouldn't be included in
+# the input cone of W and Y.
+select -set full o:W o:Y %u %ci*
+select -assert-none i:F @full %i
+select -assert-count 1 o:X %ci* i:F %i
+select -assert-count 1 o:Z %ci* i:F %i
+
+# And for unique/unique0 there should be 1 $pmux compared to the 2 $mux
+# cells without.
+select -assert-none o:W %ci* t:$pmux %i
+select -assert-none o:X %ci* t:$pmux %i
+select -assert-count 1 o:Y %ci* t:$pmux %i
+select -assert-count 1 o:Z %ci* t:$pmux %i
+
+select -assert-count 2 o:W %ci* t:$mux %i
+select -assert-count 2 o:X %ci* t:$mux %i
+select -assert-none o:Y %ci* t:$mux %i
+select -assert-none o:Z %ci* t:$mux %i
diff --git a/tests/verilog/unique_priority_if.ys b/tests/verilog/unique_priority_if.ys
new file mode 100644
index 000000000..a6053e809
--- /dev/null
+++ b/tests/verilog/unique_priority_if.ys
@@ -0,0 +1,54 @@
+read_verilog -sv << EOF
+module top (input A, B, C, D, E, F, output reg W, X, Y, Z);
+	always_comb begin
+		W = F;
+		priority if (C == A)
+			W = D;
+		else if (C == B)
+			W = E;
+	end
+
+	always_comb begin
+		X = F;
+		if (C == A)
+			X = D;
+		else if (C == B)
+			X = E;
+	end
+
+	always_comb begin
+		Y = F;
+		unique if (C == A)
+			Y = D;
+		else if (C == B)
+			Y = E;
+	end
+
+	always_comb begin
+		Z = F;
+		unique0 if (C == A)
+			Z = D;
+		else if (C == B)
+			Z = E;
+	end
+endmodule
+EOF
+prep
+# For the ones which use priority/unique, the F signal shouldn't be included in
+# the input cone of W and Y.
+select -set full o:W o:Y %u %ci*
+select -assert-none i:F @full %i
+select -assert-count 1 o:X %ci* i:F %i
+select -assert-count 1 o:Z %ci* i:F %i
+
+# And for unique/unique0 there should be 1 $pmux compared to the 2 $mux
+# cells without.
+select -assert-none o:W %ci* t:$pmux %i
+select -assert-none o:X %ci* t:$pmux %i
+select -assert-count 1 o:Y %ci* t:$pmux %i
+select -assert-count 1 o:Z %ci* t:$pmux %i
+
+select -assert-count 2 o:W %ci* t:$mux %i
+select -assert-count 2 o:X %ci* t:$mux %i
+select -assert-none o:Y %ci* t:$mux %i
+select -assert-none o:Z %ci* t:$mux %i