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Merge 4c48fc283b into 9d3d0a4336

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YoYo 2025-04-13 11:46:12 +00:00 • committed by GitHub
commit 7acdcf8206
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3 changed files with 10 additions and 4 deletions
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2
frontends/ast/genrtlil.cc
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@ -1840,8 +1840,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int width = max(width_hint, 1);
width_hint = -1, sign_hint = true;
children[0]->detectSignWidthWorker(width_hint, sign_hint);
children[1]->detectSignWidthWorker(width_hint, sign_hint);
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
children[1]->detectSignWidthWorker(width_hint, sign_hint);
RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec sig = binop2rtlil(this, type_name, width, left, right);
return sig;

5
frontends/ast/simplify.cc
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@ -2438,7 +2438,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (varbuf->type != AST_CONSTANT)
input_error("Right hand side of 1st expression of %s for-loop is not constant!\n", loop_type_str);
if (init_ast->children[0]->id2ast)
varbuf->is_signed = init_ast->children[0]->id2ast->is_signed;
else
varbuf->is_signed = init_ast->children[0]->is_signed;
auto resolved = current_scope.at(init_ast->children[0]->str);
if (resolved->range_valid) {
int const_size = varbuf->range_left - varbuf->range_right;