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fix(#4402):missing sign while for loop iteration variable is signed

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This commit is contained in:
YoYo 2024-05-26 16:19:17 +08:00
parent 5579685673
commit 4c48fc283b
3 changed files with 10 additions and 4 deletions
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7
backends/verilog/verilog_backend.cc
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@ -414,12 +414,15 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
#else
// do not use Verilog-2k "output reg" syntax in Verilog export
std::string range = "";
std::string sign = "";
if (wire->width != 1) {
if (wire->upto)
range = stringf(" [%d:%d]", wire->start_offset, wire->width - 1 + wire->start_offset);
else
range = stringf(" [%d:%d]", wire->width - 1 + wire->start_offset, wire->start_offset);
}
if (wire->is_signed)
sign = " signed ";
if (wire->port_input && !wire->port_output)
f << stringf("%s" "input%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
if (!wire->port_input && wire->port_output)
@ -427,14 +430,14 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
if (wire->port_input && wire->port_output)
f << stringf("%s" "inout%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
if (reg_wires.count(wire->name)) {
f << stringf("%s" "reg%s %s", indent.c_str(), range.c_str(), id(wire->name).c_str());
f << stringf("%s" "reg%s%s %s", indent.c_str(), sign.c_str(), range.c_str(), id(wire->name).c_str());
if (wire->attributes.count(ID::init)) {
f << stringf(" = ");
dump_const(f, wire->attributes.at(ID::init));
}
f << stringf(";\n");
} else
f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
f << stringf("%s" "wire%s%s %s;\n", indent.c_str(), sign.c_str(), range.c_str(), id(wire->name).c_str());
#endif
}

2
frontends/ast/genrtlil.cc
View file

@ -1840,8 +1840,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
int width = max(width_hint, 1);
width_hint = -1, sign_hint = true;
children[0]->detectSignWidthWorker(width_hint, sign_hint);
children[1]->detectSignWidthWorker(width_hint, sign_hint);
RTLIL::SigSpec left = children[0]->genRTLIL(width_hint, sign_hint);
children[1]->detectSignWidthWorker(width_hint, sign_hint);
RTLIL::SigSpec right = children[1]->genRTLIL(width_hint, sign_hint);
RTLIL::SigSpec sig = binop2rtlil(this, type_name, width, left, right);
return sig;

5
frontends/ast/simplify.cc
View file

@ -2380,7 +2380,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
if (varbuf->type != AST_CONSTANT)
input_error("Right hand side of 1st expression of %s for-loop is not constant!\n", loop_type_str);
if (init_ast->children[0]->id2ast)
varbuf->is_signed = init_ast->children[0]->id2ast->is_signed;
else
varbuf->is_signed = init_ast->children[0]->is_signed;
auto resolved = current_scope.at(init_ast->children[0]->str);
if (resolved->range_valid) {
int const_size = varbuf->range_left - varbuf->range_right;