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docs: several small documentation fixes.

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Gary Wong 2025-05-29 21:26:28 -06:00
parent 3ef4c91c31
commit 7a9d727bd0
4 changed files with 7 additions and 7 deletions
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docs/source/yosys_internals/flow/verilog_frontend.rst
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@ -626,7 +626,7 @@ pass and the passes it launches:
| This pass replaces the ``RTLIL::SyncRule``\ s to d-type flip-flops (with
asynchronous resets if necessary).
- | `proc_dff`
- | `proc_memwr`
| This pass replaces the ``RTLIL::MemWriteAction``\ s with `$memwr` cells.
- | `proc_clean`