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Fix mux xilinx mapping when all inputs are x

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Adrien Prost-Boucle 2025-04-06 11:43:17 +02:00
parent 98d4355b82
commit 7a1729e609
1 changed files with 10 additions and 3 deletions
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9
techlibs/xilinx/cells_map.v
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@ -184,11 +184,18 @@ module \$__XILINX_SHIFTX (A, B, Y);
assign A_i[i] = A[i*2]; assign A_i[i] = A[i*2];
\$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
end end
// Trim off any leading 1'bx -es in A // Handle presence of leading 1'bx -es in A
else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin
// Replace by 1'bx if A is only 'x
if (A_WIDTH_trimmed(A_WIDTH-1) == 0) begin
assign Y = 1'bx;
end
// Trim off any leading 1'bx -es in A
else begin
localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1); localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1);
\$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y)); \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y));
end end
end
else if (A_WIDTH < `MIN_MUX_INPUTS) begin else if (A_WIDTH < `MIN_MUX_INPUTS) begin
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;
end end