From 7a1729e60916a6dfd5a2a1c8e155ab36a50d1732 Mon Sep 17 00:00:00 2001 From: Adrien Prost-Boucle Date: Sun, 6 Apr 2025 11:43:17 +0200 Subject: [PATCH] Fix mux xilinx mapping when all inputs are x --- techlibs/xilinx/cells_map.v | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 2b8eade2f..846f03bb9 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -184,10 +184,17 @@ module \$__XILINX_SHIFTX (A, B, Y); assign A_i[i] = A[i*2]; \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); end - // Trim off any leading 1'bx -es in A + // Handle presence of leading 1'bx -es in A else if (_TECHMAP_CONSTMSK_A_[A_WIDTH-1] && _TECHMAP_CONSTVAL_A_[A_WIDTH-1] === 1'bx) begin - localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1); - \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y)); + // Replace by 1'bx if A is only 'x + if (A_WIDTH_trimmed(A_WIDTH-1) == 0) begin + assign Y = 1'bx; + end + // Trim off any leading 1'bx -es in A + else begin + localparam A_WIDTH_new = A_WIDTH_trimmed(A_WIDTH-1); + \$__XILINX_SHIFTX #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B), .Y(Y)); + end end else if (A_WIDTH < `MIN_MUX_INPUTS) begin wire _TECHMAP_FAIL_ = 1;