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Add ice40 box files

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This commit is contained in:
Eddie Hung 2019-04-16 16:39:30 -07:00
parent ae2653c50f
commit 7980118d74
6 changed files with 27 additions and 1 deletions
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3
techlibs/ice40/Makefile.inc
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@ -28,6 +28,9 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v)) $(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells.box))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_box.v))
$(eval $(call add_share_file,share/ice40,techlibs/ice40/lut.lut))
$(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh)) $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
$(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh)) $(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))

6
techlibs/ice40/cells.box Normal file
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@ -0,0 +1,6 @@
# NB: Inputs/Outputs must be ordered alphabetically
# Inputs: CI I0 I1
# Outputs: CO
SB_CARRY 1 1 3 1
126 259 231

5
techlibs/ice40/cells_box.v Normal file
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@ -0,0 +1,5 @@
(* abc_box_id = 1 *)
module SB_CARRY (output CO, input CI, I0, I1);
assign CO = (I0 && I1) || ((I0 || I1) && CI);
endmodule

1
techlibs/ice40/cells_sim.v
View file

@ -881,6 +881,7 @@ module SB_WARMBOOT (
); );
endmodule endmodule
(* nomem2reg *)
module SB_SPRAM256KA ( module SB_SPRAM256KA (
input [13:0] ADDRESS, input [13:0] ADDRESS,
input [15:0] DATAIN, input [15:0] DATAIN,

4
techlibs/ice40/lut.lut Normal file
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@ -0,0 +1,4 @@
1 1 316
2 1 316 379
3 1 316 379 400
4 1 316 379 400 449

9
techlibs/ice40/synth_ice40.cc
View file

@ -316,7 +316,14 @@ struct SynthIce40Pass : public ScriptPass
run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)"); run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
} }
if (!noabc) { if (!noabc) {
run(abc + " -dress -lut 4", "(skip if -noabc)"); if (abc == "abc9") {
run("read_verilog +/ice40/cells_box.v");
run("techmap -map +/techmap.v A:abc_box_id");
run(abc + " -dress -lut +/ice40/lut.lut -box +/ice40/cells.box", "(skip if -noabc)");
run("blackbox A:abc_box_id");
}
else
run(abc + " -lut 4", "(skip if -noabc)");
} }
run("clean"); run("clean");
if (relut || help_mode) { if (relut || help_mode) {