mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-22 19:17:55 +00:00
Code Activity

Merge pull request #30 from alaindargelas/macro_power

Browse source 
Simulation information for macro power
This commit is contained in:
Akash Levy 2024-12-04 10:01:04 -08:00 • committed by GitHub
commit 7847b1b2eb
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
3 changed files with 8 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

1
frontends/verific/verific.cc
View file

@ -3546,6 +3546,7 @@ struct VerificPass : public Pass {
// RuntimeFlags::SetVar("veri_break_loops", 0); // SILIMATE: add to avoid breaking loops
RuntimeFlags::SetVar("veri_optimize_wide_selector", 1); // SILIMATE: add to optimize wide selector
RuntimeFlags::SetVar("veri_ignore_assertion_statements", 1); // SILIMATE: add to ignore SVA/asserts
RuntimeFlags::SetVar("verilog_ignore_unnecessary_modules_in_v_files", 1); // SILIMATE: add to ignore unnecessary modules
#endif
#ifdef VERIFIC_VHDL_SUPPORT
RuntimeFlags::SetVar("vhdl_extract_dualport_rams", 0);