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Use fast path for 32-bit Const integer constructor in more places

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This commit is contained in:
Robert O'Callahan 2025-08-29 03:34:17 +00:00
parent ec52d6c649
commit 7814aa0c31
6 changed files with 10 additions and 9 deletions
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2
frontends/json/jsonparse.cc
View file

@ -258,7 +258,7 @@ Const json_parse_attr_param_value(JsonNode *node)
} }
} else } else
if (node->type == 'N') { if (node->type == 'N') {
value = Const(node->data_number, 32); value = Const(node->data_number);
if (node->data_number < 0) if (node->data_number < 0)
value.flags |= RTLIL::CONST_FLAG_SIGNED; value.flags |= RTLIL::CONST_FLAG_SIGNED;
} else } else

2
frontends/rtlil/rtlil_parser.y
View file

@ -465,7 +465,7 @@ constant:
free($1); free($1);
} | } |
TOK_INT { TOK_INT {
$$ = new RTLIL::Const($1, 32); $$ = new RTLIL::Const($1);
} | } |
TOK_STRING { TOK_STRING {
$$ = new RTLIL::Const($1); $$ = new RTLIL::Const($1);

8
frontends/verific/verific.cc
View file

@ -267,13 +267,13 @@ static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string
static const RTLIL::Const extract_vhdl_integer(std::string &val) static const RTLIL::Const extract_vhdl_integer(std::string &val)
{ {
char *end; char *end;
return RTLIL::Const((int)std::strtol(val.c_str(), &end, 10), 32); return RTLIL::Const((int)std::strtol(val.c_str(), &end, 10));
} }
static const RTLIL::Const extract_vhdl_char(std::string &val) static const RTLIL::Const extract_vhdl_char(std::string &val)
{ {
if (val.size()==3 && val[0]=='\"' && val.back()=='\"') if (val.size()==3 && val[0]=='\"' && val.back()=='\"')
return RTLIL::Const((int)val[1], 32); return RTLIL::Const((int)val[1]);
log_error("Error parsing VHDL character.\n"); log_error("Error parsing VHDL character.\n");
} }
@ -311,7 +311,7 @@ static const RTLIL::Const extract_vhdl_const(const char *value, bool output_sig
} else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) && } else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) &&
((decimal = std::strtol(value, &end, 10)), !end[0])) { ((decimal = std::strtol(value, &end, 10)), !end[0])) {
is_signed = output_signed; is_signed = output_signed;
c = RTLIL::Const((int)decimal, 32); c = RTLIL::Const((int)decimal);
} else if (val == "false") { } else if (val == "false") {
c = RTLIL::Const::from_string("0"); c = RTLIL::Const::from_string("0");
} else if (val == "true") { } else if (val == "true") {
@ -344,7 +344,7 @@ static const RTLIL::Const extract_verilog_const(const char *value, bool allow_s
} else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) && } else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) &&
((decimal = std::strtol(value, &end, 10)), !end[0])) { ((decimal = std::strtol(value, &end, 10)), !end[0])) {
is_signed = output_signed; is_signed = output_signed;
c = RTLIL::Const((int)decimal, 32); c = RTLIL::Const((int)decimal);
} else if (allow_string) { } else if (allow_string) {
c = RTLIL::Const(val); c = RTLIL::Const(val);
} else { } else {

3
kernel/rtlil.h
View file

@ -1013,7 +1013,8 @@ struct RTLIL::SigChunk
SigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {} SigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}
SigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {} SigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}
SigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {} SigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}
SigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {} SigChunk(int val) /*default width 32*/ : SigChunk(RTLIL::Const(val)) {}
SigChunk(int val, int width) : SigChunk(RTLIL::Const(val, width)) {}
SigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {} SigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}
SigChunk(const RTLIL::SigBit &bit); SigChunk(const RTLIL::SigBit &bit);

2
techlibs/ice40/ice40_dsp.cc
View file

@ -82,7 +82,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
SigSpec CD = st.sigCD; SigSpec CD = st.sigCD;
if (CD.empty()) if (CD.empty())
CD = RTLIL::Const(0, 32); CD = RTLIL::Const(0);
else else
log_assert(GetSize(CD) == 32); log_assert(GetSize(CD) == 32);

2
techlibs/quicklogic/ql_bram_merge.cc
View file

@ -45,7 +45,7 @@ struct QlBramMergeWorker {
{ {
if(cell->type != split_cell_type) continue; if(cell->type != split_cell_type) continue;
if(!cell->hasParam(ID(OPTION_SPLIT))) continue; if(!cell->hasParam(ID(OPTION_SPLIT))) continue;
if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue; if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1)) continue;
mergeable_groups[get_key(cell)].insert(cell); mergeable_groups[get_key(cell)].insert(cell);
} }
} }