diff --git a/frontends/json/jsonparse.cc b/frontends/json/jsonparse.cc
index 1aab81015..0c5547f18 100644
--- a/frontends/json/jsonparse.cc
+++ b/frontends/json/jsonparse.cc
@@ -258,7 +258,7 @@ Const json_parse_attr_param_value(JsonNode *node)
 		}
 	} else
 	if (node->type == 'N') {
-		value = Const(node->data_number, 32);
+		value = Const(node->data_number);
 		if (node->data_number < 0)
 			value.flags |= RTLIL::CONST_FLAG_SIGNED;
 	} else
diff --git a/frontends/rtlil/rtlil_parser.y b/frontends/rtlil/rtlil_parser.y
index 4f0fb3b97..2b8d7b7ab 100644
--- a/frontends/rtlil/rtlil_parser.y
+++ b/frontends/rtlil/rtlil_parser.y
@@ -465,7 +465,7 @@ constant:
 		free($1);
 	} |
 	TOK_INT {
-		$$ = new RTLIL::Const($1, 32);
+		$$ = new RTLIL::Const($1);
 	} |
 	TOK_STRING {
 		$$ = new RTLIL::Const($1);
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 7284c7cd9..503dcc022 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -267,13 +267,13 @@ static const RTLIL::Const extract_vhdl_bit_vector(std::string &val, std::string
 static const RTLIL::Const extract_vhdl_integer(std::string &val)
 {
 	char *end;
-	return RTLIL::Const((int)std::strtol(val.c_str(), &end, 10), 32);
+	return RTLIL::Const((int)std::strtol(val.c_str(), &end, 10));
 }
 
 static const RTLIL::Const extract_vhdl_char(std::string &val)
 {
 	if (val.size()==3 && val[0]=='\"' && val.back()=='\"')
-		return RTLIL::Const((int)val[1], 32);
+		return RTLIL::Const((int)val[1]);
 	log_error("Error parsing VHDL character.\n");
 }
 
@@ -311,7 +311,7 @@ static const  RTLIL::Const extract_vhdl_const(const char *value, bool output_sig
 	} else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) &&
 			((decimal = std::strtol(value, &end, 10)), !end[0])) {
 		is_signed = output_signed;
-		c = RTLIL::Const((int)decimal, 32);
+		c = RTLIL::Const((int)decimal);
 	} else if (val == "false") {
 		c = RTLIL::Const::from_string("0");
 	} else if (val == "true") {
@@ -344,7 +344,7 @@ static const  RTLIL::Const extract_verilog_const(const char *value, bool allow_s
 	} else if ((value[0] == '-' || (value[0] >= '0' && value[0] <= '9')) &&
 			((decimal = std::strtol(value, &end, 10)), !end[0])) {
 		is_signed = output_signed;
-		c = RTLIL::Const((int)decimal, 32);
+		c = RTLIL::Const((int)decimal);
 	} else if (allow_string) {
 		c = RTLIL::Const(val);
 	} else {
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index db407939e..77e3540ac 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1013,7 +1013,8 @@ struct RTLIL::SigChunk
 	SigChunk(RTLIL::Wire *wire) : wire(wire), width(GetSize(wire)), offset(0) {}
 	SigChunk(RTLIL::Wire *wire, int offset, int width = 1) : wire(wire), width(width), offset(offset) {}
 	SigChunk(const std::string &str) : SigChunk(RTLIL::Const(str)) {}
-	SigChunk(int val, int width = 32) : SigChunk(RTLIL::Const(val, width)) {}
+	SigChunk(int val) /*default width 32*/ : SigChunk(RTLIL::Const(val)) {}
+	SigChunk(int val, int width) : SigChunk(RTLIL::Const(val, width)) {}
 	SigChunk(RTLIL::State bit, int width = 1) : SigChunk(RTLIL::Const(bit, width)) {}
 	SigChunk(const RTLIL::SigBit &bit);
 
diff --git a/techlibs/ice40/ice40_dsp.cc b/techlibs/ice40/ice40_dsp.cc
index 3f00028c3..995cdb97e 100644
--- a/techlibs/ice40/ice40_dsp.cc
+++ b/techlibs/ice40/ice40_dsp.cc
@@ -82,7 +82,7 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
 
 	SigSpec CD = st.sigCD;
 	if (CD.empty())
-		CD = RTLIL::Const(0, 32);
+		CD = RTLIL::Const(0);
 	else
 		log_assert(GetSize(CD) == 32);
 
diff --git a/techlibs/quicklogic/ql_bram_merge.cc b/techlibs/quicklogic/ql_bram_merge.cc
index bed1ba572..7b99d74e5 100644
--- a/techlibs/quicklogic/ql_bram_merge.cc
+++ b/techlibs/quicklogic/ql_bram_merge.cc
@@ -45,7 +45,7 @@ struct QlBramMergeWorker {
 		{
 			if(cell->type != split_cell_type) continue;
 			if(!cell->hasParam(ID(OPTION_SPLIT))) continue;
-			if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue;
+			if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1)) continue;
 			mergeable_groups[get_key(cell)].insert(cell);
 		}
 	}