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Merge 0a15a23e8f into 63b3ce0c77

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Emil J 2025-04-04 04:08:16 +13:00 committed by GitHub
parent 63b3ce0c77 0a15a23e8f
commit 77d1a36dd2
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1 changed files with 56 additions and 32 deletions
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88
passes/opt/opt_expr.cc
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@ -30,6 +30,7 @@ USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
bool did_something;
int sort_fails = 0;
void replace_undriven(RTLIL::Module *module, const CellTypes &ct)
{
@ -125,7 +126,6 @@ void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell *cell,
log_debug("Replacing %s cell `%s' (%s) in module `%s' with constant driver `%s = %s'.\n",
cell->type.c_str(), cell->name.c_str(), info.c_str(),
module->name.c_str(), log_signal(Y), log_signal(out_val));
// log_cell(cell);
assign_map.add(Y, out_val);
module->connect(Y, out_val);
module->remove(cell);
@ -393,7 +393,7 @@ int get_highest_hot_index(RTLIL::SigSpec signal)
return -1;
}
void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool noclkinv)
void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool consume_x, bool mux_undef, bool mux_bool, bool do_fine, bool keepdc, bool noclkinv, int effort)
{
SigMap assign_map(module);
dict<RTLIL::SigSpec, RTLIL::SigSpec> invert_map;
@ -490,35 +490,50 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
handle_clkpol_celltype_swap(cell, "$_DLATCHSR_??N_", "$_DLATCHSR_??P_", ID::R, assign_map, invert_map);
}
TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
dict<RTLIL::SigBit, Cell*> outbit_to_cell;
std::vector<Cell*> module_cells = module->cells();
auto visitor = [&](auto&& do_action) {
if (sort_fails >= effort) {
for (auto cell : module_cells)
if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type))
do_action(cell);
} else {
TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
dict<RTLIL::SigBit, Cell*> outbit_to_cell;
for (auto cell : module->cells())
if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) {
for (auto &conn : cell->connections())
if (yosys_celltypes.cell_output(cell->type, conn.first))
for (auto bit : assign_map(conn.second))
outbit_to_cell[bit] = cell;
cells.node(cell);
}
for (auto cell : module->cells())
if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) {
for (auto &conn : cell->connections())
if (yosys_celltypes.cell_output(cell->type, conn.first))
for (auto bit : assign_map(conn.second))
outbit_to_cell[bit] = cell;
cells.node(cell);
}
for (auto cell : module->cells())
if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) {
const int r_index = cells.node(cell);
for (auto &conn : cell->connections())
if (yosys_celltypes.cell_input(cell->type, conn.first))
for (auto bit : assign_map(conn.second))
if (outbit_to_cell.count(bit))
cells.edge(cells.node(outbit_to_cell.at(bit)), r_index);
}
for (auto cell : module->cells())
if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type)) {
const int r_index = cells.node(cell);
for (auto &conn : cell->connections())
if (yosys_celltypes.cell_input(cell->type, conn.first))
for (auto bit : assign_map(conn.second))
if (outbit_to_cell.count(bit))
cells.edge(cells.node(outbit_to_cell.at(bit)), r_index);
}
if (!cells.sort()) {
// There might be a combinational loop, or there might be constants on the output of cells. 'check' may find out more.
// ...unless this is a coarse-grained cell loop, but not a bit loop, in which case it won't, and all is good.
log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", log_id(module));
}
for (auto cell : cells.sorted)
if (!cells.sort()) {
// There might be a combinational loop, or there might be constants on the output of cells. 'check' may find out more.
// ...unless this is a coarse-grained cell loop, but not a bit loop, in which case it won't, and all is good.
log("Couldn't topologically sort cells, optimizing module %s may take a longer time.\n", log_id(module));
sort_fails++;
if (sort_fails >= effort)
log("Effort of %d exceeded, no longer attempting toposort on module %s.\n",
effort, log_id(module));
}
for (auto cell : cells.sorted) {
do_action(cell);
}
}
};
visitor([&](auto& cell)
{
#define ACTION_DO(_p_, _s_) do { cover("opt.opt_expr.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
#define ACTION_DO_Y(_v_) ACTION_DO(ID::Y, RTLIL::SigSpec(RTLIL::State::S ## _v_))
@ -2233,7 +2248,7 @@ skip_alu_split:
#undef ACTION_DO_Y
#undef FOLD_1ARG_CELL
#undef FOLD_2ARG_CELL
}
});
}
void replace_const_connections(RTLIL::Module *module) {
@ -2288,6 +2303,10 @@ struct OptExprPass : public Pass {
log(" all result bits to be set to x. this behavior changes when 'a+0' is\n");
log(" replaced by 'a'. the -keepdc option disables all such optimizations.\n");
log("\n");
log(" -effort N\n");
log(" allow toposort to fail in N iterations on each module before giving up\n");
log(" on sorting for that module. Default value is 5\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
@ -2297,7 +2316,7 @@ struct OptExprPass : public Pass {
bool noclkinv = false;
bool do_fine = false;
bool keepdc = false;
int effort = 5;
log_header(design, "Executing OPT_EXPR pass (perform const folding).\n");
log_push();
@ -2334,6 +2353,10 @@ struct OptExprPass : public Pass {
keepdc = true;
continue;
}
if (args[argidx] == "-effort" && argidx + 1 < args.size()) {
effort = atoi(args[++argidx].c_str());
continue;
}
break;
}
extra_args(args, argidx, design);
@ -2350,15 +2373,16 @@ struct OptExprPass : public Pass {
design->scratchpad_set_bool("opt.did_something", true);
}
sort_fails = 0;
do {
do {
did_something = false;
replace_const_cells(design, module, false /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv);
replace_const_cells(design, module, false /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv, effort);
if (did_something)
design->scratchpad_set_bool("opt.did_something", true);
} while (did_something);
if (!keepdc)
replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv);
replace_const_cells(design, module, true /* consume_x */, mux_undef, mux_bool, do_fine, keepdc, noclkinv, effort);
if (did_something)
design->scratchpad_set_bool("opt.did_something", true);
} while (did_something);