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opt_expr: neater variable names, avoid shadowing

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This commit is contained in:
Emil J. Tywoniak 2025-03-20 12:31:59 +01:00
parent 89b12e4898
commit 0a15a23e8f
1 changed files with 4 additions and 4 deletions
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8
passes/opt/opt_expr.cc
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@ -491,11 +491,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
}
std::vector<Cell*> module_cells = module->cells();
auto iterator = [&](auto&& replace_cell) {
auto visitor = [&](auto&& do_action) {
if (sort_fails >= effort) {
for (auto cell : module_cells)
if (design->selected(module, cell) && yosys_celltypes.cell_evaluable(cell->type))
replace_cell(cell);
do_action(cell);
} else {
TopoSort<RTLIL::Cell*, RTLIL::IdString::compare_ptr_by_name<RTLIL::Cell>> cells;
dict<RTLIL::SigBit, Cell*> outbit_to_cell;
@ -529,11 +529,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
effort, log_id(module));
}
for (auto cell : cells.sorted) {
replace_cell(cell);
do_action(cell);
}
}
};
iterator([&](auto& cell)
visitor([&](auto& cell)
{
#define ACTION_DO(_p_, _s_) do { cover("opt.opt_expr.action_" S__LINE__); replace_cell(assign_map, module, cell, input.as_string(), _p_, _s_); goto next_cell; } while (0)
#define ACTION_DO_Y(_v_) ACTION_DO(ID::Y, RTLIL::SigSpec(RTLIL::State::S ## _v_))