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Tests: Use setattr -setstr
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parent
4006dafefc
commit
7630e24bbf
5 changed files with 25 additions and 25 deletions
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@ -19,14 +19,14 @@ select -assert-count 9 t:TRELLIS_DPR16X4
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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setattr -setstr syn_ramstyle block_ram m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "Block_RAM" m:memory
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setattr -setstr syn_ramstyle Block_RAM m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD # any case works
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@ -41,7 +41,7 @@ select -assert-count 9 t:TRELLIS_DPR16X4
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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setattr -setstr syn_ramstyle registers m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # requested FFRAM explicitly
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select -assert-count 180 t:TRELLIS_FF
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@ -98,14 +98,14 @@ select -assert-count 5 t:TRELLIS_DPR16X4
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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setattr -setstr syn_ramstyle block_ram m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "Block_RAM" m:memory
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setattr -setstr syn_ramstyle Block_RAM m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:DP16KD # any case works
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@ -120,7 +120,7 @@ select -assert-count 5 t:TRELLIS_DPR16X4
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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setattr -setstr syn_ramstyle registers m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:DP16KD # requested FFRAM explicitly
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select -assert-count 90 t:TRELLIS_FF
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@ -146,14 +146,14 @@ select -assert-count 1 t:TRELLIS_DPR16X4
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "distributed" m:memory
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setattr -setstr syn_ramstyle distributed m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:TRELLIS_DPR16X4
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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setattr -setstr syn_ramstyle registers m:memory
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synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
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select -assert-count 68 t:TRELLIS_FF
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@ -187,7 +187,7 @@ select -assert-min 18 t:LUT4
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
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hierarchy -top sync_rom
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setattr -set syn_romstyle "ebr" m:memory
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setattr -setstr syn_romstyle ebr m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:DP16KD
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@ -201,7 +201,7 @@ select -assert-count 1 t:DP16KD
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
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hierarchy -top sync_rom
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setattr -set syn_romstyle "logic" m:memory
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setattr -setstr syn_romstyle logic m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:DP16KD # requested LUTROM explicitly
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select -assert-min 18 t:LUT4
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@ -234,7 +234,7 @@ select -assert-min 9 t:LUT4
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
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hierarchy -top sync_rom
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setattr -set syn_romstyle "ebr" m:memory
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setattr -setstr syn_romstyle ebr m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 1 t:DP16KD
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@ -248,7 +248,7 @@ select -assert-count 1 t:DP16KD
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
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hierarchy -top sync_rom
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setattr -set syn_romstyle "logic" m:memory
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setattr -setstr syn_romstyle logic m:memory
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synth_ecp5 -top sync_rom; cd sync_rom
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select -assert-count 0 t:DP16KD # requested LUTROM explicitly
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select -assert-min 9 t:LUT4
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