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Tests: Use setattr -setstr

This commit is contained in:
Krystine Sherwin 2025-10-06 11:38:55 +13:00
parent 4006dafefc
commit 7630e24bbf
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5 changed files with 25 additions and 25 deletions

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@ -19,14 +19,14 @@ select -assert-count 9 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "block_ram" m:memory
setattr -setstr syn_ramstyle block_ram m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:DP16KD
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "Block_RAM" m:memory
setattr -setstr syn_ramstyle Block_RAM m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:DP16KD # any case works
@ -41,7 +41,7 @@ select -assert-count 9 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "registers" m:memory
setattr -setstr syn_ramstyle registers m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:DP16KD # requested FFRAM explicitly
select -assert-count 180 t:TRELLIS_FF
@ -98,14 +98,14 @@ select -assert-count 5 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "block_ram" m:memory
setattr -setstr syn_ramstyle block_ram m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:DP16KD
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "Block_RAM" m:memory
setattr -setstr syn_ramstyle Block_RAM m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:DP16KD # any case works
@ -120,7 +120,7 @@ select -assert-count 5 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "registers" m:memory
setattr -setstr syn_ramstyle registers m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:DP16KD # requested FFRAM explicitly
select -assert-count 90 t:TRELLIS_FF
@ -146,14 +146,14 @@ select -assert-count 1 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "distributed" m:memory
setattr -setstr syn_ramstyle distributed m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "registers" m:memory
setattr -setstr syn_ramstyle registers m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
select -assert-count 68 t:TRELLIS_FF
@ -187,7 +187,7 @@ select -assert-min 18 t:LUT4
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
hierarchy -top sync_rom
setattr -set syn_romstyle "ebr" m:memory
setattr -setstr syn_romstyle ebr m:memory
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 1 t:DP16KD
@ -201,7 +201,7 @@ select -assert-count 1 t:DP16KD
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
hierarchy -top sync_rom
setattr -set syn_romstyle "logic" m:memory
setattr -setstr syn_romstyle logic m:memory
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 0 t:DP16KD # requested LUTROM explicitly
select -assert-min 18 t:LUT4
@ -234,7 +234,7 @@ select -assert-min 9 t:LUT4
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
hierarchy -top sync_rom
setattr -set syn_romstyle "ebr" m:memory
setattr -setstr syn_romstyle ebr m:memory
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 1 t:DP16KD
@ -248,7 +248,7 @@ select -assert-count 1 t:DP16KD
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
hierarchy -top sync_rom
setattr -set syn_romstyle "logic" m:memory
setattr -setstr syn_romstyle logic m:memory
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 0 t:DP16KD # requested LUTROM explicitly
select -assert-min 9 t:LUT4