diff --git a/tests/arch/ecp5/memories.ys b/tests/arch/ecp5/memories.ys
index f075182c8..904be565b 100644
--- a/tests/arch/ecp5/memories.ys
+++ b/tests/arch/ecp5/memories.ys
@@ -19,14 +19,14 @@ select -assert-count 9 t:TRELLIS_DPR16X4
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
 hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "block_ram" m:memory
+setattr -setstr syn_ramstyle block_ram m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
 hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "Block_RAM" m:memory
+setattr -setstr syn_ramstyle Block_RAM m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD # any case works
 
@@ -41,7 +41,7 @@ select -assert-count 9 t:TRELLIS_DPR16X4
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
 hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "registers" m:memory
+setattr -setstr syn_ramstyle registers m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:DP16KD # requested FFRAM explicitly
 select -assert-count 180 t:TRELLIS_FF
@@ -98,14 +98,14 @@ select -assert-count 5 t:TRELLIS_DPR16X4
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
 hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "block_ram" m:memory
+setattr -setstr syn_ramstyle block_ram m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
 
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
 hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "Block_RAM" m:memory
+setattr -setstr syn_ramstyle Block_RAM m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD # any case works
 
@@ -120,7 +120,7 @@ select -assert-count 5 t:TRELLIS_DPR16X4
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
 hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "registers" m:memory
+setattr -setstr syn_ramstyle registers m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:DP16KD # requested FFRAM explicitly
 select -assert-count 90 t:TRELLIS_FF
@@ -146,14 +146,14 @@ select -assert-count 1 t:TRELLIS_DPR16X4
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
 hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "distributed" m:memory
+setattr -setstr syn_ramstyle distributed m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:TRELLIS_DPR16X4
 
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
 hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "registers" m:memory
+setattr -setstr syn_ramstyle registers m:memory
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
 select -assert-count 68 t:TRELLIS_FF
@@ -187,7 +187,7 @@ select -assert-min 18 t:LUT4
 design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
 hierarchy -top sync_rom
-setattr -set syn_romstyle "ebr" m:memory
+setattr -setstr syn_romstyle ebr m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:DP16KD
 
@@ -201,7 +201,7 @@ select -assert-count 1 t:DP16KD
 design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
 hierarchy -top sync_rom
-setattr -set syn_romstyle "logic" m:memory
+setattr -setstr syn_romstyle logic m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:DP16KD # requested LUTROM explicitly
 select -assert-min 18 t:LUT4
@@ -234,7 +234,7 @@ select -assert-min 9 t:LUT4
 design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
 hierarchy -top sync_rom
-setattr -set syn_romstyle "ebr" m:memory
+setattr -setstr syn_romstyle ebr m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 1 t:DP16KD
 
@@ -248,7 +248,7 @@ select -assert-count 1 t:DP16KD
 design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
 hierarchy -top sync_rom
-setattr -set syn_romstyle "logic" m:memory
+setattr -setstr syn_romstyle logic m:memory
 synth_ecp5 -top sync_rom; cd sync_rom
 select -assert-count 0 t:DP16KD # requested LUTROM explicitly
 select -assert-min 9 t:LUT4
diff --git a/tests/arch/ice40/memories.ys b/tests/arch/ice40/memories.ys
index d480a3abe..c2eb5924d 100644
--- a/tests/arch/ice40/memories.ys
+++ b/tests/arch/ice40/memories.ys
@@ -37,14 +37,14 @@ select -assert-min 1 t:SB_DFFE
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
 hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "block_ram" m:memory
+setattr -setstr syn_ramstyle block_ram m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
 
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
 hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "Block_RAM" m:memory
+setattr -setstr syn_ramstyle Block_RAM m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K # any case works
 
@@ -58,7 +58,7 @@ select -assert-count 1 t:SB_RAM40_4K
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
 hierarchy -top sync_ram_sdp
-setattr -set syn_ramstyle "registers" m:memory
+setattr -setstr syn_ramstyle registers m:memory
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
 select -assert-min 1 t:SB_DFFE
@@ -110,7 +110,7 @@ select -assert-min 1 t:SB_LUT4
 design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
 hierarchy -top sync_rom
-setattr -set syn_romstyle "ebr" m:memory
+setattr -setstr syn_romstyle ebr m:memory
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 1 t:SB_RAM40_4K
 
@@ -124,7 +124,7 @@ select -assert-count 1 t:SB_RAM40_4K
 design -reset; read_verilog -defer ../common/blockrom.v
 chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
 hierarchy -top sync_rom
-setattr -set syn_romstyle "logic" m:memory
+setattr -setstr syn_romstyle logic m:memory
 synth_ice40 -top sync_rom; cd sync_rom
 select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
 select -assert-min 1 t:SB_LUT4
diff --git a/tests/arch/xilinx/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys
index 74861850f..7d1a54537 100644
--- a/tests/arch/xilinx/attributes_test.ys
+++ b/tests/arch/xilinx/attributes_test.ys
@@ -16,7 +16,7 @@ select -assert-count 1 t:RAM32M
 # Set ram_style distributed to blockram memory; will be implemented as distributed
 design -reset
 read_verilog ../common/memory_attributes/attributes_test.v
-setattr -set ram_style "distributed" block_ram/m:*
+setattr -setstr ram_style distributed block_ram/m:*
 synth_xilinx -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 16 t:RAM256X1S
diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys
index c2b7aede7..474fecf9b 100644
--- a/tests/arch/xilinx/blockram.ys
+++ b/tests/arch/xilinx/blockram.ys
@@ -51,7 +51,7 @@ select -assert-count 1 t:RAMB36E1
 design -reset
 read_verilog ../common/blockram.v
 hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 
-setattr -set ram_style "block" m:memory
+setattr -setstr ram_style block m:memory
 synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB18E1
@@ -67,7 +67,7 @@ select -assert-count 0 t:RAMB18E1
 design -reset
 read_verilog ../common/blockram.v
 hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
-setattr -set ram_style "block" m:memory
+setattr -setstr ram_style block m:memory
 synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB18E1
diff --git a/tests/techmap/clkbufmap.ys b/tests/techmap/clkbufmap.ys
index abe830109..8cac96fc7 100644
--- a/tests/techmap/clkbufmap.ys
+++ b/tests/techmap/clkbufmap.ys
@@ -82,7 +82,7 @@ select -assert-count 0 w:clk2 %a %co t:clkbuf %i
 
 design -load ref
 setattr -set clkbuf_inhibit 1 w:clk1
-setattr -set buffer_type "bufg" w:clk2
+setattr -setstr buffer_type bufg w:clk2
 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
 select -assert-count 3 top/t:clkbuf
 select -assert-count 3 sub/t:clkbuf
@@ -98,10 +98,10 @@ select -assert-count 1 @clk2 %x:+[o] %co c:s1 %i    # And that one fanout is 's0
 # ----------------------
 
 design -load ref
-setattr -set buffer_type "none" w:clk1
-setattr -set buffer_type "bufr" w:clk2
-setattr -set buffer_type "bufr" w:sclk4
-setattr -set buffer_type "bufr" w:sclk5
+setattr -setstr buffer_type none w:clk1
+setattr -setstr buffer_type bufr w:clk2
+setattr -setstr buffer_type bufr w:sclk4
+setattr -setstr buffer_type bufr w:sclk5
 clkbufmap -buf clkbuf o:i w:* a:buffer_type=none a:buffer_type=bufr %u %d
 select -assert-count 0 w:clk1 %a %co t:clkbuf %i
 select -assert-count 0 w:clk2 %a %co t:clkbuf %i