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Tests: Use setattr -setstr

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Krystine Sherwin 2025-10-06 11:38:55 +13:00
parent 4006dafefc
commit 7630e24bbf
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5 changed files with 25 additions and 25 deletions
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24
tests/arch/ecp5/memories.ys
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@ -19,14 +19,14 @@ select -assert-count 9 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "block_ram" m:memory
setattr -setstr syn_ramstyle block_ram m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:DP16KD
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "Block_RAM" m:memory
setattr -setstr syn_ramstyle Block_RAM m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:DP16KD # any case works
@ -41,7 +41,7 @@ select -assert-count 9 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "registers" m:memory
setattr -setstr syn_ramstyle registers m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:DP16KD # requested FFRAM explicitly
select -assert-count 180 t:TRELLIS_FF
@ -98,14 +98,14 @@ select -assert-count 5 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "block_ram" m:memory
setattr -setstr syn_ramstyle block_ram m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:DP16KD
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "Block_RAM" m:memory
setattr -setstr syn_ramstyle Block_RAM m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:DP16KD # any case works
@ -120,7 +120,7 @@ select -assert-count 5 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "registers" m:memory
setattr -setstr syn_ramstyle registers m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:DP16KD # requested FFRAM explicitly
select -assert-count 90 t:TRELLIS_FF
@ -146,14 +146,14 @@ select -assert-count 1 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "distributed" m:memory
setattr -setstr syn_ramstyle distributed m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:TRELLIS_DPR16X4
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 4 -set DATA_WIDTH 4 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "registers" m:memory
setattr -setstr syn_ramstyle registers m:memory
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:TRELLIS_DPR16X4 # requested FFRAM explicitly
select -assert-count 68 t:TRELLIS_FF
@ -187,7 +187,7 @@ select -assert-min 18 t:LUT4
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 36 sync_rom
hierarchy -top sync_rom
setattr -set syn_romstyle "ebr" m:memory
setattr -setstr syn_romstyle ebr m:memory
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 1 t:DP16KD
@ -201,7 +201,7 @@ select -assert-count 1 t:DP16KD
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 36 sync_rom
hierarchy -top sync_rom
setattr -set syn_romstyle "logic" m:memory
setattr -setstr syn_romstyle logic m:memory
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 0 t:DP16KD # requested LUTROM explicitly
select -assert-min 18 t:LUT4
@ -234,7 +234,7 @@ select -assert-min 9 t:LUT4
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 18 sync_rom
hierarchy -top sync_rom
setattr -set syn_romstyle "ebr" m:memory
setattr -setstr syn_romstyle ebr m:memory
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 1 t:DP16KD
@ -248,7 +248,7 @@ select -assert-count 1 t:DP16KD
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 3 -set DATA_WIDTH 18 sync_rom
hierarchy -top sync_rom
setattr -set syn_romstyle "logic" m:memory
setattr -setstr syn_romstyle logic m:memory
synth_ecp5 -top sync_rom; cd sync_rom
select -assert-count 0 t:DP16KD # requested LUTROM explicitly
select -assert-min 9 t:LUT4

10
tests/arch/ice40/memories.ys
View file

@ -37,14 +37,14 @@ select -assert-min 1 t:SB_DFFE
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "block_ram" m:memory
setattr -setstr syn_ramstyle block_ram m:memory
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "Block_RAM" m:memory
setattr -setstr syn_ramstyle Block_RAM m:memory
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:SB_RAM40_4K # any case works
@ -58,7 +58,7 @@ select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
hierarchy -top sync_ram_sdp
setattr -set syn_ramstyle "registers" m:memory
setattr -setstr syn_ramstyle registers m:memory
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
select -assert-min 1 t:SB_DFFE
@ -110,7 +110,7 @@ select -assert-min 1 t:SB_LUT4
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
hierarchy -top sync_rom
setattr -set syn_romstyle "ebr" m:memory
setattr -setstr syn_romstyle ebr m:memory
synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 1 t:SB_RAM40_4K
@ -124,7 +124,7 @@ select -assert-count 1 t:SB_RAM40_4K
design -reset; read_verilog -defer ../common/blockrom.v
chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
hierarchy -top sync_rom
setattr -set syn_romstyle "logic" m:memory
setattr -setstr syn_romstyle logic m:memory
synth_ice40 -top sync_rom; cd sync_rom
select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
select -assert-min 1 t:SB_LUT4

2
tests/arch/xilinx/attributes_test.ys
View file

@ -16,7 +16,7 @@ select -assert-count 1 t:RAM32M
# Set ram_style distributed to blockram memory; will be implemented as distributed
design -reset
read_verilog ../common/memory_attributes/attributes_test.v
setattr -set ram_style "distributed" block_ram/m:*
setattr -setstr ram_style distributed block_ram/m:*
synth_xilinx -top block_ram -noiopad
cd block_ram # Constrain all select calls below inside the top module
select -assert-count 16 t:RAM256X1S

4
tests/arch/xilinx/blockram.ys
View file

@ -51,7 +51,7 @@ select -assert-count 1 t:RAMB36E1
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1
setattr -set ram_style "block" m:memory
setattr -setstr ram_style block m:memory
synth_xilinx -top sync_ram_sdp -noiopad
cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1
@ -67,7 +67,7 @@ select -assert-count 0 t:RAMB18E1
design -reset
read_verilog ../common/blockram.v
hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
setattr -set ram_style "block" m:memory
setattr -setstr ram_style block m:memory
synth_xilinx -top sync_ram_sdp -noiopad
cd sync_ram_sdp
select -assert-count 1 t:RAMB18E1