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	fmt: rudimentary %m support (= %l)
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					 4 changed files with 34 additions and 0 deletions
				
			
		|  | @ -291,6 +291,9 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik | ||||||
| 						} else if (fmt.substr(i, 2) == "%l" || fmt.substr(i, 2) == "%L") { | 						} else if (fmt.substr(i, 2) == "%l" || fmt.substr(i, 2) == "%L") { | ||||||
| 							i++; | 							i++; | ||||||
| 							part.str += module_name.str(); | 							part.str += module_name.str(); | ||||||
|  | 						} else if (fmt.substr(i, 2) == "%m" || fmt.substr(i, 2) == "%M") { | ||||||
|  | 							i++; | ||||||
|  | 							part.str += module_name.str(); | ||||||
| 						} else { | 						} else { | ||||||
| 							if (!part.str.empty()) { | 							if (!part.str.empty()) { | ||||||
| 								part.type = FmtPart::STRING; | 								part.type = FmtPart::STRING; | ||||||
|  |  | ||||||
							
								
								
									
										12
									
								
								tests/fmt/display_lm.v
									
										
									
									
									
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										12
									
								
								tests/fmt/display_lm.v
									
										
									
									
									
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							|  | @ -0,0 +1,12 @@ | ||||||
|  | module top; | ||||||
|  |     mid mid_uut (); | ||||||
|  | endmodule | ||||||
|  | 
 | ||||||
|  | module mid (); | ||||||
|  |     bot bot_uut (); | ||||||
|  | endmodule | ||||||
|  | 
 | ||||||
|  | module bot (); | ||||||
|  |     initial $display("%%l: %l\n%%m: %m"); | ||||||
|  |     always $display("%%l: %l\n%%m: %m"); | ||||||
|  | endmodule | ||||||
							
								
								
									
										10
									
								
								tests/fmt/display_lm_tb.cc
									
										
									
									
									
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								tests/fmt/display_lm_tb.cc
									
										
									
									
									
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							|  | @ -0,0 +1,10 @@ | ||||||
|  | #include <iostream> | ||||||
|  | #include "yosys-display_lm.cc" | ||||||
|  | 
 | ||||||
|  | int main() | ||||||
|  | { | ||||||
|  | 	cxxrtl_design::p_top uut; | ||||||
|  | 
 | ||||||
|  |     uut.step(); | ||||||
|  |     return 0; | ||||||
|  | } | ||||||
|  | @ -53,3 +53,12 @@ ${CXX:-g++} -o yosys-always_full -I../.. always_full_tb.cc | ||||||
| iverilog -o iverilog-always_full always_full.v always_full_tb.v | iverilog -o iverilog-always_full always_full.v always_full_tb.v | ||||||
| ./iverilog-always_full | awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $0}' >iverilog-always_full.log | ./iverilog-always_full | awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $0}' >iverilog-always_full.log | ||||||
| diff iverilog-always_full.log yosys-always_full.log | diff iverilog-always_full.log yosys-always_full.log | ||||||
|  | 
 | ||||||
|  | ../../yosys -p "read_verilog display_lm.v" >yosys-display_lm.log | ||||||
|  | ../../yosys -p "read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc" | ||||||
|  | ${CXX:-g++} -o yosys-display_lm_cc -I../.. display_lm_tb.cc | ||||||
|  | ./yosys-display_lm_cc >yosys-display_lm_cc.log | ||||||
|  | for log in yosys-display_lm.log yosys-display_lm_cc.log; do | ||||||
|  | 	grep "^%l: \\\\bot\$" "$log" | ||||||
|  | 	grep "^%m: \\\\bot\$" "$log" | ||||||
|  | done | ||||||
|  |  | ||||||
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