From 75b44f21d1ff0c79f64e4ec3d2c10d4bb93fdefe Mon Sep 17 00:00:00 2001
From: Charlotte <charlotte@hrzn.ee>
Date: Wed, 28 Jun 2023 11:51:21 +1000
Subject: [PATCH] fmt: rudimentary %m support (= %l)

---
 kernel/fmt.cc              |  3 +++
 tests/fmt/display_lm.v     | 12 ++++++++++++
 tests/fmt/display_lm_tb.cc | 10 ++++++++++
 tests/fmt/run-test.sh      |  9 +++++++++
 4 files changed, 34 insertions(+)
 create mode 100644 tests/fmt/display_lm.v
 create mode 100644 tests/fmt/display_lm_tb.cc

diff --git a/kernel/fmt.cc b/kernel/fmt.cc
index d72d60ba8..9d9e95ac3 100644
--- a/kernel/fmt.cc
+++ b/kernel/fmt.cc
@@ -291,6 +291,9 @@ void Fmt::parse_verilog(const std::vector<VerilogFmtArg> &args, bool sformat_lik
 						} else if (fmt.substr(i, 2) == "%l" || fmt.substr(i, 2) == "%L") {
 							i++;
 							part.str += module_name.str();
+						} else if (fmt.substr(i, 2) == "%m" || fmt.substr(i, 2) == "%M") {
+							i++;
+							part.str += module_name.str();
 						} else {
 							if (!part.str.empty()) {
 								part.type = FmtPart::STRING;
diff --git a/tests/fmt/display_lm.v b/tests/fmt/display_lm.v
new file mode 100644
index 000000000..d96f233f0
--- /dev/null
+++ b/tests/fmt/display_lm.v
@@ -0,0 +1,12 @@
+module top;
+    mid mid_uut ();
+endmodule
+
+module mid ();
+    bot bot_uut ();
+endmodule
+
+module bot ();
+    initial $display("%%l: %l\n%%m: %m");
+    always $display("%%l: %l\n%%m: %m");
+endmodule
diff --git a/tests/fmt/display_lm_tb.cc b/tests/fmt/display_lm_tb.cc
new file mode 100644
index 000000000..ebc62f80f
--- /dev/null
+++ b/tests/fmt/display_lm_tb.cc
@@ -0,0 +1,10 @@
+#include <iostream>
+#include "yosys-display_lm.cc"
+
+int main()
+{
+	cxxrtl_design::p_top uut;
+
+    uut.step();
+    return 0;
+}
diff --git a/tests/fmt/run-test.sh b/tests/fmt/run-test.sh
index aa9c8fe7b..2568e2776 100644
--- a/tests/fmt/run-test.sh
+++ b/tests/fmt/run-test.sh
@@ -53,3 +53,12 @@ ${CXX:-g++} -o yosys-always_full -I../.. always_full_tb.cc
 iverilog -o iverilog-always_full always_full.v always_full_tb.v
 ./iverilog-always_full | awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $0}' >iverilog-always_full.log
 diff iverilog-always_full.log yosys-always_full.log
+
+../../yosys -p "read_verilog display_lm.v" >yosys-display_lm.log
+../../yosys -p "read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc"
+${CXX:-g++} -o yosys-display_lm_cc -I../.. display_lm_tb.cc
+./yosys-display_lm_cc >yosys-display_lm_cc.log
+for log in yosys-display_lm.log yosys-display_lm_cc.log; do
+	grep "^%l: \\\\bot\$" "$log"
+	grep "^%m: \\\\bot\$" "$log"
+done