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Collapse signed*signed or combined nodes via BW.

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This commit is contained in:
nella 2026-05-18 17:21:26 +02:00
parent 73fe179a26
commit 749d6cd8f7
4 changed files with 210 additions and 35 deletions
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7
tests/arith_tree/arith_tree_fma.ys
View file

@ -100,7 +100,7 @@ select -assert-min 1 t:$macc t:$macc_v2 %u
design -reset
read_verilog <<EOT
module fma_signed_bailout(
module fma_signed(
input signed [3:0] a, b,
input signed [7:0] c,
output signed [7:0] y
@ -114,6 +114,7 @@ alumacc
opt
equiv_opt arith_tree
design -load postopt
select -assert-count 0 t:$fa
select -assert-min 1 t:$macc t:$macc_v2 %u
select -assert-count 0 t:$macc t:$macc_v2 %u
select -assert-count 0 t:$mul
select -assert-min 1 t:$fa
design -reset

135
tests/arith_tree/arith_tree_signed_fma.ys Normal file
View file

@ -0,0 +1,135 @@
read_verilog <<EOT
module signed_mac(
input signed [3:0] a, b,
input signed [7:0] c,
output signed [7:0] y
);
assign y = a * b + c;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
equiv_opt arith_tree
design -load postopt
select -assert-count 0 t:$macc t:$macc_v2 %u
select -assert-count 0 t:$mul
select -assert-min 1 t:$fa
design -reset
read_verilog <<EOT
module signed_mul(
input signed [3:0] a, b,
output signed [7:0] y
);
assign y = a * b;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
equiv_opt arith_tree
design -load postopt
select -assert-count 0 t:$macc t:$macc_v2 %u
select -assert-count 0 t:$mul
select -assert-min 1 t:$fa
design -reset
read_verilog <<EOT
module signed_dot2(
input signed [3:0] a, b, c, d,
output signed [7:0] y
);
assign y = a * b + c * d;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
equiv_opt arith_tree
design -load postopt
select -assert-count 0 t:$macc t:$macc_v2 %u
select -assert-count 0 t:$mul
select -assert-min 1 t:$fa
design -reset
read_verilog <<EOT
module signed_mac_sub(
input signed [3:0] a, b,
input signed [7:0] c,
output signed [7:0] y
);
assign y = a * b - c;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
equiv_opt arith_tree
design -load postopt
select -assert-count 0 t:$macc t:$macc_v2 %u
select -assert-count 0 t:$mul
select -assert-min 1 t:$fa
design -reset
read_verilog <<EOT
module signed_mac_negprod(
input signed [3:0] a, b,
input signed [7:0] c,
output signed [7:0] y
);
assign y = c - a * b;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
equiv_opt arith_tree
design -load postopt
select -assert-count 0 t:$macc t:$macc_v2 %u
select -assert-min 1 t:$fa
design -reset
read_verilog <<EOT
module signed_mac_wide(
input signed [7:0] a, b,
input signed [15:0] c,
output signed [15:0] y
);
assign y = a * b + c;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
equiv_opt arith_tree
design -load postopt
select -assert-count 0 t:$macc t:$macc_v2 %u
select -assert-count 0 t:$mul
select -assert-min 1 t:$fa
design -reset
read_verilog <<EOT
module signed_mac_nofma(
input signed [3:0] a, b,
input signed [7:0] c,
output signed [7:0] y
);
assign y = a * b + c;
endmodule
EOT
hierarchy -auto-top
proc
alumacc
opt
equiv_opt arith_tree -no-fma
design -load postopt
select -assert-count 0 t:$fa
select -assert-min 1 t:$macc t:$macc_v2 %u
design -reset