mirror of
https://github.com/YosysHQ/yosys
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135 lines
2.3 KiB
Text
135 lines
2.3 KiB
Text
read_verilog <<EOT
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module signed_mac(
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input signed [3:0] a, b,
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input signed [7:0] c,
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output signed [7:0] y
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);
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assign y = a * b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 0 t:$macc t:$macc_v2 %u
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select -assert-count 0 t:$mul
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select -assert-min 1 t:$fa
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design -reset
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read_verilog <<EOT
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module signed_mul(
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input signed [3:0] a, b,
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output signed [7:0] y
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);
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assign y = a * b;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 0 t:$macc t:$macc_v2 %u
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select -assert-count 0 t:$mul
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select -assert-min 1 t:$fa
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design -reset
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read_verilog <<EOT
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module signed_dot2(
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input signed [3:0] a, b, c, d,
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output signed [7:0] y
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);
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assign y = a * b + c * d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 0 t:$macc t:$macc_v2 %u
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select -assert-count 0 t:$mul
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select -assert-min 1 t:$fa
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design -reset
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read_verilog <<EOT
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module signed_mac_sub(
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input signed [3:0] a, b,
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input signed [7:0] c,
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output signed [7:0] y
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);
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assign y = a * b - c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 0 t:$macc t:$macc_v2 %u
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select -assert-count 0 t:$mul
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select -assert-min 1 t:$fa
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design -reset
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read_verilog <<EOT
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module signed_mac_negprod(
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input signed [3:0] a, b,
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input signed [7:0] c,
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output signed [7:0] y
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);
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assign y = c - a * b;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 0 t:$macc t:$macc_v2 %u
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select -assert-min 1 t:$fa
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design -reset
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read_verilog <<EOT
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module signed_mac_wide(
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input signed [7:0] a, b,
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input signed [15:0] c,
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output signed [15:0] y
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);
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assign y = a * b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 0 t:$macc t:$macc_v2 %u
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select -assert-count 0 t:$mul
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select -assert-min 1 t:$fa
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design -reset
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read_verilog <<EOT
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module signed_mac_nofma(
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input signed [3:0] a, b,
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input signed [7:0] c,
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output signed [7:0] y
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);
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assign y = a * b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree -no-fma
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design -load postopt
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select -assert-count 0 t:$fa
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select -assert-min 1 t:$macc t:$macc_v2 %u
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design -reset
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