3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-06 22:23:23 +00:00

Switching example synth to fifo

Fifo code based on SBY quick start.
Instead of showing the full design we are (currently) focusing on a single output (rdata), using `%ci*` to get the subcircuit it relies on.
This commit is contained in:
Krystine Sherwin 2023-12-18 13:19:01 +13:00
parent 80c78aaad6
commit 742ec78ca3
No known key found for this signature in database
9 changed files with 2538 additions and 326 deletions

View file

@ -0,0 +1,16 @@
PROGRAM_PREFIX :=
YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys
DOTS = addr_gen_hier.dot addr_gen_proc.dot
DOTS += rdata_proc.dot rdata_flat.dot
DOTS += fifo_flat.dot fifo_synth.dot
dots: $(DOTS) fifo.out
$(DOTS) fifo.out: fifo.v fifo.ys
$(YOSYS) fifo.ys -l fifo.out -Q
.PHONY: clean
clean:
rm -f *.dot