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Test.
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nella
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122
tests/arith_tree/arith_tree_42.ys
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122
tests/arith_tree/arith_tree_42.ys
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@ -0,0 +1,122 @@
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read_verilog <<EOT
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module four_op_42(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -strategy 42
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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select -assert-count 2 t:$fa c:*emit_compressor_42* %i
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select -assert-count 0 t:$fa c:*emit_compressor_32* %i
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design -reset
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read_verilog <<EOT
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module four_op_fa(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -strategy fa
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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select -assert-count 0 t:$fa c:*emit_compressor_42* %i
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select -assert-count 2 t:$fa c:*emit_compressor_32* %i
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design -reset
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read_verilog <<EOT
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module eight_op_42(
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input [3:0] a, b, c, d, e, f, g, h,
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output [3:0] y
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);
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assign y = a + b + c + d + e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -strategy 42
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design -load postopt
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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select -assert-min 1 t:$fa c:*emit_compressor_42* %i
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design -reset
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read_verilog <<EOT
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module sixteen_op_42(
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input [3:0] a0, a1, a2, a3, a4, a5, a6, a7,
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input [3:0] a8, a9, a10, a11, a12, a13, a14, a15,
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output [3:0] y
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);
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assign y = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7
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+ a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -strategy 42
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design -load postopt
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select -assert-count 14 t:$fa
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select -assert-count 1 t:$add
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select -assert-min 1 t:$fa c:*emit_compressor_42* %i
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design -reset
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read_verilog <<EOT
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module five_op_42(
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input [3:0] a, b, c, d, e,
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output [3:0] y
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);
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assign y = a + b + c + d + e;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -strategy 42
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design -load postopt
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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select -assert-min 1 t:$fa c:*emit_compressor_42* %i
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design -reset
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read_verilog <<EOT
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module six_op_42(
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input [3:0] a, b, c, d, e, f,
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output [3:0] y
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);
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assign y = a + b + c + d + e + f;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -strategy 42
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design -load postopt
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select -assert-count 4 t:$fa
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select -assert-count 1 t:$add
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select -assert-min 1 t:$fa c:*emit_compressor_42* %i
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design -reset
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read_verilog <<EOT
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module seven_op_42(
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input [3:0] a, b, c, d, e, f, g,
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output [3:0] y
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);
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assign y = a + b + c + d + e + f + g;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -strategy 42
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design -load postopt
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select -assert-count 5 t:$fa
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select -assert-count 1 t:$add
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select -assert-min 1 t:$fa c:*emit_compressor_42* %i
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design -reset
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78
tests/arith_tree/arith_tree_defaults.ys
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78
tests/arith_tree/arith_tree_defaults.ys
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@ -0,0 +1,78 @@
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# Idempotence
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read_verilog <<EOT
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module idem_add4(
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input [3:0] a, b, c, d,
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output [3:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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arith_tree
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module idem_mac(
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input [3:0] a, b,
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input [7:0] c,
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output [7:0] y
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);
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assign y = a * b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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arith_tree
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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select -assert-count 0 t:$macc t:$macc_v2 %u
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select -assert-count 0 t:$mul
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arith_tree
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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select -assert-count 0 t:$macc t:$macc_v2 %u
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select -assert-count 0 t:$mul
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design -reset
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read_verilog <<EOT
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module default_smoke(
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input [15:0] a, b, c, d,
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output [15:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 2 t:$fa c:*emit_compressor_42* %i
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select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
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design -reset
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read_verilog <<EOT
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module default_narrow(
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input [14:0] a, b, c, d,
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output [14:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 2 t:$fa
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select -assert-count 2 t:$fa c:*emit_compressor_42* %i
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select -assert-count 1 t:$add
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select -assert-count 0 t:$add a:adder_arch %i
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design -reset
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@ -217,6 +217,26 @@ alumacc
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opt
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arith_tree
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opt_clean
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select -assert-none t:$macc t:$macc_v2 %u
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select -assert-none t:$mul
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select -assert-count 7 t:$fa
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select -assert-min 1 t:$fa c:*emit_compressor_42* %i
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design -reset
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read_verilog <<EOT
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module macc_mul_nofma(
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input [7:0] a, b, c,
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output [15:0] y
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);
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assign y = a * b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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arith_tree -no-fma
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opt_clean
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select -assert-none t:$fa
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select -assert-min 1 t:$macc t:$macc_v2 %u
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design -reset
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@ -402,6 +422,26 @@ alumacc
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opt
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arith_tree
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opt_clean
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select -assert-none t:$macc t:$macc_v2 %u
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select -assert-none t:$mul
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select -assert-count 8 t:$fa
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select -assert-min 1 t:$fa c:*emit_compressor_42* %i
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design -reset
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read_verilog <<EOT
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module macc_mul_survives_nofma(
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input [7:0] a, b, c, d,
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output [15:0] y
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);
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assign y = a * b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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arith_tree -no-fma
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opt_clean
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select -assert-none t:$fa
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select -assert-min 1 t:$macc t:$macc_v2 %u
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design -reset
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97
tests/arith_tree/arith_tree_final_adder.ys
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97
tests/arith_tree/arith_tree_final_adder.ys
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@ -0,0 +1,97 @@
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read_verilog <<EOT
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module final_auto_wide(
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input [31:0] a, b, c, d,
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output [31:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -final auto
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
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design -reset
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read_verilog <<EOT
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module final_auto_narrow(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -final auto
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 2 t:$fa
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select -assert-count 0 t:$add a:adder_arch %i
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design -reset
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read_verilog <<EOT
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module final_ripple(
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input [31:0] a, b, c, d,
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output [31:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -final ripple
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design -load postopt
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select -assert-count 1 t:$add
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select -assert-count 0 t:$add a:adder_arch %i
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design -reset
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read_verilog <<EOT
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module final_prefix_narrow(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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equiv_opt arith_tree -final prefix
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design -load postopt
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select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
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design -reset
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read_verilog <<EOT
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module final_elarith(
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input [15:0] a, b, c, d,
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output [15:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree -final elarith
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select -assert-count 0 t:$add
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select -assert-count 1 t:\AddCfast
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select -assert-count 2 t:$fa
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select -assert-count 2 t:$fa c:*emit_compressor_42* %i
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design -reset
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read_verilog <<EOT
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module elarith_macro(
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input [15:0] a, b, c, d,
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output [15:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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arith_tree -elarith-macro
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select -assert-count 0 t:$fa
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select -assert-count 0 t:$add
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select -assert-count 1 t:\AddMopCsv
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design -reset
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119
tests/arith_tree/arith_tree_fma.ys
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119
tests/arith_tree/arith_tree_fma.ys
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@ -0,0 +1,119 @@
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read_verilog <<EOT
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module fma_mul_only(
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input [3:0] a, b,
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output [7:0] y
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);
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assign y = a * b;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 0 t:$macc t:$macc_v2 %u
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select -assert-count 0 t:$mul
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select -assert-count 1 t:$add
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select -assert-min 1 t:$fa
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design -reset
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read_verilog <<EOT
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module fma_mac(
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input [3:0] a, b,
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input [7:0] c,
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output [7:0] y
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);
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assign y = a * b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 0 t:$macc t:$macc_v2 %u
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select -assert-count 0 t:$mul
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select -assert-count 1 t:$add
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select -assert-min 1 t:$fa
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design -reset
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read_verilog <<EOT
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module fma_dot2(
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input [3:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a * b + c * d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 0 t:$macc t:$macc_v2 %u
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select -assert-count 0 t:$mul
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select -assert-count 1 t:$add
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select -assert-min 1 t:$fa
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design -reset
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read_verilog <<EOT
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module fma_mac_sub(
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input [3:0] a, b,
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input [7:0] c,
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output [7:0] y
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);
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assign y = a * b - c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 0 t:$macc t:$macc_v2 %u
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select -assert-count 0 t:$mul
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select -assert-count 1 t:$add
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select -assert-min 1 t:$fa
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design -reset
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read_verilog <<EOT
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module fma_disabled(
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input [3:0] a, b,
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input [7:0] c,
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output [7:0] y
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);
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assign y = a * b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree -no-fma
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design -load postopt
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select -assert-count 0 t:$fa
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select -assert-min 1 t:$macc t:$macc_v2 %u
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design -reset
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read_verilog <<EOT
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module fma_signed_bailout(
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input signed [3:0] a, b,
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input signed [7:0] c,
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output signed [7:0] y
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);
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assign y = a * b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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equiv_opt arith_tree
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design -load postopt
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select -assert-count 0 t:$fa
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select -assert-min 1 t:$macc t:$macc_v2 %u
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design -reset
|
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