diff --git a/tests/arith_tree/arith_tree_42.ys b/tests/arith_tree/arith_tree_42.ys
new file mode 100644
index 000000000..75951ab5e
--- /dev/null
+++ b/tests/arith_tree/arith_tree_42.ys
@@ -0,0 +1,122 @@
+read_verilog <<EOT
+module four_op_42(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -strategy 42
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 2 t:$fa c:*emit_compressor_42* %i
+select -assert-count 0 t:$fa c:*emit_compressor_32* %i
+design -reset
+
+read_verilog <<EOT
+module four_op_fa(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -strategy fa
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 0 t:$fa c:*emit_compressor_42* %i
+select -assert-count 2 t:$fa c:*emit_compressor_32* %i
+design -reset
+
+read_verilog <<EOT
+module eight_op_42(
+	input [3:0] a, b, c, d, e, f, g, h,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -strategy 42
+design -load postopt
+select -assert-count 6 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module sixteen_op_42(
+	input [3:0] a0, a1, a2, a3, a4, a5, a6, a7,
+	input [3:0] a8, a9, a10, a11, a12, a13, a14, a15,
+	output [3:0] y
+);
+	assign y = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7
+	        + a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -strategy 42
+design -load postopt
+select -assert-count 14 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module five_op_42(
+	input [3:0] a, b, c, d, e,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -strategy 42
+design -load postopt
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module six_op_42(
+	input [3:0] a, b, c, d, e, f,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e + f;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -strategy 42
+design -load postopt
+select -assert-count 4 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module seven_op_42(
+	input [3:0] a, b, c, d, e, f, g,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e + f + g;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -strategy 42
+design -load postopt
+select -assert-count 5 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
diff --git a/tests/arith_tree/arith_tree_defaults.ys b/tests/arith_tree/arith_tree_defaults.ys
new file mode 100644
index 000000000..1fb73e82e
--- /dev/null
+++ b/tests/arith_tree/arith_tree_defaults.ys
@@ -0,0 +1,78 @@
+# Idempotence
+read_verilog <<EOT
+module idem_add4(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+arith_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+arith_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module idem_mac(
+	input [3:0] a, b,
+	input [7:0] c,
+	output [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+arith_tree
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+arith_tree
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+design -reset
+
+read_verilog <<EOT
+module default_smoke(
+	input [15:0] a, b, c, d,
+	output [15:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 2 t:$fa c:*emit_compressor_42* %i
+select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
+design -reset
+
+read_verilog <<EOT
+module default_narrow(
+	input [14:0] a, b, c, d,
+	output [14:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 2 t:$fa c:*emit_compressor_42* %i
+select -assert-count 1 t:$add
+select -assert-count 0 t:$add a:adder_arch %i
+design -reset
diff --git a/tests/arith_tree/arith_tree_edge_cases.ys b/tests/arith_tree/arith_tree_edge_cases.ys
index fd40f2aa7..280b5d09c 100644
--- a/tests/arith_tree/arith_tree_edge_cases.ys
+++ b/tests/arith_tree/arith_tree_edge_cases.ys
@@ -217,6 +217,26 @@ alumacc
 opt
 arith_tree
 opt_clean
+select -assert-none t:$macc t:$macc_v2 %u
+select -assert-none t:$mul
+select -assert-count 7 t:$fa
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module macc_mul_nofma(
+	input [7:0] a, b, c,
+	output [15:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+arith_tree -no-fma
+opt_clean
 select -assert-none t:$fa
 select -assert-min 1 t:$macc t:$macc_v2 %u
 design -reset
@@ -402,6 +422,26 @@ alumacc
 opt
 arith_tree
 opt_clean
+select -assert-none t:$macc t:$macc_v2 %u
+select -assert-none t:$mul
+select -assert-count 8 t:$fa
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module macc_mul_survives_nofma(
+	input [7:0] a, b, c, d,
+	output [15:0] y
+);
+	assign y = a * b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+arith_tree -no-fma
+opt_clean
 select -assert-none t:$fa
 select -assert-min 1 t:$macc t:$macc_v2 %u
 design -reset
diff --git a/tests/arith_tree/arith_tree_final_adder.ys b/tests/arith_tree/arith_tree_final_adder.ys
new file mode 100644
index 000000000..b4d5824cc
--- /dev/null
+++ b/tests/arith_tree/arith_tree_final_adder.ys
@@ -0,0 +1,97 @@
+read_verilog <<EOT
+module final_auto_wide(
+	input [31:0] a, b, c, d,
+	output [31:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -final auto
+design -load postopt
+select -assert-count 1 t:$add
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
+design -reset
+
+read_verilog <<EOT
+module final_auto_narrow(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -final auto
+design -load postopt
+select -assert-count 1 t:$add
+select -assert-count 2 t:$fa
+select -assert-count 0 t:$add a:adder_arch %i
+design -reset
+
+read_verilog <<EOT
+module final_ripple(
+	input [31:0] a, b, c, d,
+	output [31:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -final ripple
+design -load postopt
+select -assert-count 1 t:$add
+select -assert-count 0 t:$add a:adder_arch %i
+design -reset
+
+read_verilog <<EOT
+module final_prefix_narrow(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -final prefix
+design -load postopt
+select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
+design -reset
+
+read_verilog <<EOT
+module final_elarith(
+	input [15:0] a, b, c, d,
+	output [15:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+arith_tree -final elarith
+select -assert-count 0 t:$add
+select -assert-count 1 t:\AddCfast
+select -assert-count 2 t:$fa
+select -assert-count 2 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module elarith_macro(
+	input [15:0] a, b, c, d,
+	output [15:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+arith_tree -elarith-macro
+select -assert-count 0 t:$fa
+select -assert-count 0 t:$add
+select -assert-count 1 t:\AddMopCsv
+design -reset
diff --git a/tests/arith_tree/arith_tree_fma.ys b/tests/arith_tree/arith_tree_fma.ys
new file mode 100644
index 000000000..16d90c528
--- /dev/null
+++ b/tests/arith_tree/arith_tree_fma.ys
@@ -0,0 +1,119 @@
+read_verilog <<EOT
+module fma_mul_only(
+	input [3:0] a, b,
+	output [7:0] y
+);
+	assign y = a * b;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module fma_mac(
+	input [3:0] a, b,
+	input [7:0] c,
+	output [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module fma_dot2(
+	input [3:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a * b + c * d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module fma_mac_sub(
+	input [3:0] a, b,
+	input [7:0] c,
+	output [7:0] y
+);
+	assign y = a * b - c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module fma_disabled(
+	input [3:0] a, b,
+	input [7:0] c,
+	output [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree -no-fma
+design -load postopt
+select -assert-count 0 t:$fa
+select -assert-min 1 t:$macc t:$macc_v2 %u
+design -reset
+
+read_verilog <<EOT
+module fma_signed_bailout(
+	input signed [3:0] a, b,
+	input signed [7:0] c,
+	output signed [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$fa
+select -assert-min 1 t:$macc t:$macc_v2 %u
+design -reset